= WARP v1 and WARP v2: Connecting RF and Sampling Clocks =
On WARP v1 and v2, the clocking for RF and sampling are generated by the clock board south of the FPGA. This clock board provides a number of connectors to drive clock inputs on the rest of the WARP hardware (see the [wiki:HardwareUsersGuides/ClockBoard_v1.1 Clock Board User Guide] for details). A WARP kit can be validly clocked any number of ways, but releases of reference designs such as [wiki:OFDMReferenceDesign the OFDM Reference Design] and [wiki:WARPLab] conform to a certain clocking convention. In this page, we detail this convention so users can ensure the clocking of their hardware is compatible with these designs.
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== RF Clocking ==
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[[Image(rf_clock.png,width=300)]]
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[attachment:rf_clock.png Enlarge]
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The RF clocking uses the thick, black RF cables with MMCX connectors at either end. This clock feeds the radio and allows it to tune to a user-programmable center frequency. This figure at the right shows the visual representation of how the RF clocking cables should be connected from radio boards to the clock board. The following table provides the details.
||= =||= '''Connector Reference''' =||= '''Cable Length''' =||
|| Radio Slot 1 || Radio J7 → Clock J6 || 3 inch ||
|| Radio Slot 2 || Radio J7 → Clock J10 || 2.5 inch ||
|| Radio Slot 3 || Radio J7 → Clock J11 || 3 inch ||
|| Radio Slot 4 || Radio J7 → Clock J12 || 4 inch ||
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== Sample Clocking ==
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