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I've run sysgen2opb and WARP OPB Export Tool on the OFDM_TXRX_MIMO peripheral in the OFDM Reference design V.04 (which includes Chipscope also). My question is:
a) What your WARP OPB Export compilation target does different from the standard Xilinx HDL or NGC compilation targets?
b) Which file is the translated .ngc file? Does the tool outputs it? In other words, does it run translate Xilinx ngbuild? In your PlatfromSupport/CustomPeriherals the pcore/ *.bbd indicates only ofdm_txrx_mimo.ngc as the black box.
Thanks,
Eugen
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a) The OPB Export target is a Xilinx tool, originally introduced with xapp264; this application note explains the basic flow. We wrote sysgen2opb to automate the process of constructing the OPB interface in the Sysgen model. We also extended the OPB Export tool to include support for parameterized memory address ranges and to copy the source model, init scripts and ChipScope signal descriptions into the pcore's mdlsrc folder. This extended version is what we call the WARP OPB Export tool.
b) The OPB Export Tool does not call ngdbuild. Its output is a pcore with both an HDL description (a wrapped version of the normal Sysgen HDL output) and a bunch of netlists (the usual collection of EDN and NGC files produced by Sysgen). You can see this collection of files in the /pcores/ofdm_TxRx_mimo_opbw_v1_25_b/ directory of the OFDM reference design.
The black-boxed pcore in /PlatfromSupport/CustomPeriherals/ is a copy of the post-ngdbuild core extracted from an old EDK project's implementation directory. You can find the comparable file in the reference design (/implementation/ofdm_txrx_mimo_opbw_0_wrapper.ngc). One problem with using this netslit is the core's base memory address is essentially hard-coded; the C_BASEADDR generic was given a value in the VHDL wrapper, then the full wrapper was synthesized/translated. It would be possible to build a netlist for the core one level down to avoid this, but we haven't done so. Instead, we use the pcore as generated by sysgen2opb/OPB Export (just like the reference design).
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I should also mention that the OFDM PHY pcore creation isn't totally automatic. The WARP OPB Export tool can create only basic MPD files (a restriction imposed by psfutil, the EDK utility that creates MPD files from HDL). The PHY requires some extra MPD directives that must be added manually.
From the OFDM reference design PHY core's MPD, the following lines are edited by hand:
BUS_INTERFACE BUS = PORTB, BUS_STD = XIL_BRAM, BUS_TYPE = INITIATOR ... PORT rx_int_badpkt = "", DIR = O, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_HIGH, INTERRUPT_PRIORITY = HIGH PORT rx_int_goodpkt = "", DIR = O, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_HIGH, INTERRUPT_PRIORITY = HIGH
The BUS_INTERFACE line declares the packet buffer's BRAM interface.
The SIGIS (and related) directives identify the two interrupt outputs from the PHY. The ports are declared in the default MPD, but must be identified as interrupts for the EDK tools to handle them properly.
You can read more about the MPD file format and available directives in the EDK's Platform Specification Format Reference Manual (also installed with the EDK, at $XILINX_EDK/doc/usenglish/psf_rm.pdf).
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Thank you very much for the details. I've noticed that the lines are missing from the MPD, but I believed that I missed something in the desing flow.
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I'm using the sysgen2opb and WARP Export Tool as per July 31, 2007, and it seems that they don't support rellocatable peripherals. Yes, by using p_select block, one can set the memory range the peripheral has to be mapped to, however that is a hardcoded value. Even more, when I looked in the *_opbw.vhd file, I noticed that the the opb_addr is "XOR" with the C_BASEADDR, which basically will make the peripheral always addressable only at base address 0x0. On short, I've strived for a while to access the Warp peripherals without success. It was only after commenting out the "xor C_BASEADDR" code, I could access the peripheral registers at addresses other than 0x0.
Do you have an updated sysgen2opb and/or WARP OPB Export tools which would correct this code generation or even better, to support rellocatable (from EDK) peripherals? Otherwise it would be impossible to use multiple instances of the same peripheral, as the workshop's Lab2 indicates (i.e. multiple adder models).
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The XOR code and p_select block base address of 0x0 work together to enable relocatable cores. The p_select block's parameters should be left with their default values. The base address specified here is always 0x0. The size is auto-computed by sysgen2opb based on the number of registers and shared memory spaces in the design. The p_select block enables the OPB interface whenever it observes an address with a value of 0 in the more significant bits of the OPB address line; the number of bits it compares is defined by the Sysgen core's memory size.
The XOR in the VHDL code makes this work. It presents the Sysgen core with a memory address value which will have 0 in the top bits only when the top bits of the actual OPB address match the C_BASEADDR generic value specified in the core's instantiation.
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I'd changed the p_select address selection because xapp264 indicated that. Doing that, the peripheral selection didn't work because of the "xor C_BASEADDRESS" and that caused me to believe it's something wrong with the code generation in *_opbw.vhd.
Only now I've fully understood the meaning of your statement that the WARP OPB Export compilation target was improved by making the peripheral rellocatable and 'opb_addr xor C_BASEADDRESS" is a smart and simple idea to achieve that. And yes. I've tested and it's working for me too :)
Thanks for reply.
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I'd also noticed that the following lines have to be manually added to ofdm_txrx_mimo .mpd file in addition to the:
BUS_INTERFACE BUS = PORTB, BUS_STD = XIL_BRAM, BUS_TYPE = INITIATOR
PORT bram_addr = BRAM_Addr, DIR = O, VEC = [0:31], BUS = PORTB
PORT bram_datain = BRAM_Din, DIR = I, VEC = [0:63], BUS = PORTB
PORT bram_dout = BRAM_Dout, DIR = O, VEC = [0:63], BUS = PORTB
PORT bram_reset = BRAM_Rst, DIR = O, BUS = PORTB
PORT bram_wen = BRAM_WEN, DIR = O, VEC = [0:7], BUS = PORTB
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You're right. Those ports will be part of the default MPD, but the signal assignments (the names to the right of the '=') and the BUS = PORTB need to be added manually (in addition to the changes described in post #3 above).
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