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Hi,
I have some questions regarding to the sample rate.
Q1. What is the I, Q sample rate?? Is it 50 msps?? or it is 40 msps??
Q2. For the reference design 04, what is the rssi adc sample rate?? Some places it says 25 msps, some places it says 20 msps. What is the relative sample rate between IQ and rssi??
Q3. Is there any issues with sample rate of 60 msps for the I and Q??
Thank you very much!
Regards,
Lotus
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In reference designs through v04, the I/Q ADC and DAC were clocked at 50MHz. This clock was driven by the FPGA, derived (via a DCM) from a 100MHz oscillator on the FPGA board. Starting with with v05, the sampling clock is 40MHz and is sourced from the clock board, avoiding the jitter introduced by passing it through a DCM.
The over-the-air bandwidth is determined by the PHY. In our reference designs, the PHY uses 4x interpolation/decimation filters at the I/Q inputs and outputs. So in designs through v04, the bandwidth was 12.5MHz (50 / 4). In v05, it is 10MHz (40 / 4). We will eventually increase this to 20MHz, though meeting timing will be more difficult.
The RSSI ADC clock is always driven by the FPGA via the daughtercard connectors. In our designs, we use a version of the sampling clock divided down by 4. This is for convenience in synchronizing the various blocks. The only limitation imposed by the hardware is the AD9200's (RSSI ADC) maximum sampling rate of 20MSps.
Both the I/Q ADC and DAC could run at 60MHz. The MAX2829's maximum bandwidth is only 40MHz however, so there would be oversampling. Also, the clock board doesn't provide a 60MHz clock, so a custom clock source would be required.
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