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Hello,
This is a question regarding the timing of the packet detector and the IQ data. Due to hardware limitations, we needed to model the RSSI input in the FPGA. This block has a transport delay of 40 samples. As a result, we may need to delay the IQ data by an appropriate amount. Do you have any simulations that show the Packet detection signal in relation to when the IQ data is available, or can you provide any information regarding the tming of the IQ data in releation to the packet detection signal.
Any help is greatly appreciated,
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We don't have a good simulation model for the full I/Q and RSSI -> packet detection and PHY chain. As I recall, in an operating link the packet detection signal goes high almost coincident with the first non-noise I/Q values at the input to the PHY.
But the PHY is very forgiving of errors in coarse packet detection. Because we only use the preamble's short symbols for AGC and DC offset correction (both in ofdm_agc_mimo), the packet detector can trigger anywhere in the first few short symbols. The eventual packet timing is refined by correlation against the preamble's long symbols, and this correlation can occur anywhere in a wide time range after coarse detection.
This range can even be adjusted. The control system in the Rx PHY has a programmable delay on the external packet detection signal ('ofdmRx_PktDet_Delay' in 'OFDM Rx MIMO/Packet Timing Control'). You can adjust this value to advance/delay the Rx state machine relative to the external packet detection signal. I would suggest simulating a few examples of the PHY, altering the timing of the I/Q and external packet detection signal, and finding values of this delay that work with your RSSI model.
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