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Hi,
We wanted to confirm the data at various stages of a known packet in simunlation to what we're sending in the real hardware. We are currently trying to verify the transmitted packet. We have gotten everything to match except the last part of the packet whcih we assume is the full rate payload part. In order to match the hardware we thought we need to byte reverse the subcarrier_masks in the ofdm_tx_mimo_init script. Is it true? We also modified the SymCounts to match our known transmitted packet. Is there any other configuration settings that we should be looking at?
We were looking at the CRC and we found that it is calculated in the ofdm_tx_mimo_init script. It mentions that in the hardware the CRC will be appeneded to the end of the packet. Why is that the case only in hardware? Wouldn't that be the case for simulation too?
Thank you very much for your help!
Lotus
Last edited by Lotus Yi (2007-Oct-23 13:44:38)
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I don't quite understand the question- what are you trying to match to simulation- observations of something in hardware?
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Hi,
Yes, we are trying to match the simulation outputs to the captured signals in the hardware. We are currently trying to verify the transmitted packet. In the simulation, we are observing at the outputs of the polyphase interpolators in the subsystem 'OFDM Tx MIMO/Filter & DACs'. When comparing with the captured signal in the hardware, we noticed that the last part of the packet doesn't match, which we assume is the full rate payload part of the packet. We modified the Tx_OFDM_SymCounts register value in the ofdm_tx_mimo_init script to match our known transmitted packet. We also byte reversed the subcarrier_masks in the ofdm_tx_mimo_init script. Is it right? Is there any other settings we should be looking at?
Also, in the ofdm_tx_mimo_init script, it mentions "In hardware, the checksum automatically over-writes the last four bytes of the payload". Why is this the case in the hardware as opposed to simulation where the CRC is calculated beforehand?
Thank you very much for your help!
Lotus
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I would suggest looking at the PHY initialization in WARPMAC and WARPPHY. The code there sets the values of most of the registers in the PHY. If you want the simulation to match hardware sample-by-sample, you will need to verify that your C and M code initialize every PHY register with matching values.
Also, in the ofdm_tx_mimo_init script, it mentions "In hardware, the checksum automatically over-writes the last four bytes of the payload". Why is this the case in the hardware as opposed to simulation where the CRC is calculated beforehand?
The checksum overwrites the last four bytes of the payload in simulation as well; by "in hardware", I meant the CRC is calculated in logic, as opposed to requiring the MAC to calculate it in software.
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Hi,
Thank you very much for you help. We have resolved our issues. We now have the simulation results and captured singals in the hardware matched. The problem was that the exteranl bram that is connected to TxRx block wasn't enabled and clocked. Once we connected a clock to the bram and enable it, we were able to to see the matched results.
Lotus
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