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I get the following errors when I hit "Generate Bitstream" while working thru the XPS Intro tutorial (http://warp.rice.edu/trac/wiki/Exercise … neratingHW):
-----------------------------------------------------------------------------------------------
Running XST synthesis ...
INFO:MDT - The following instances are synthesized with XST. The MPD option
IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.
IPNAME:ppc405_0_wrapper INSTANCE:ppc405_0 -
C:\safe\working\fpga_designs\warp_intro\system.mhs line 39 - Running XST
synthesis
WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 59
days, this program will not operate. For more information about this product,
please refer to the Evaluation Agreement, which was shipped to you along with
the Evaluation CDs.
To purchase an annual license for this software, please contact your local
Field Applications Engineer (FAE) or salesperson. If you have any questions,
or if we can assist in any way, please send an email to: eval@xilinx.com
Thank You!
ERROR:MDT - Aborting XST flow execution...
INFO:MDT - Refer to
C:\safe\working\fpga_designs\warp_intro\synthesis\ppc405_0_wrapper_xst.srp
for details
ERROR:MDT - platgen failed with errors!
make: *** [implementation/system.bmm] Error 2
Done!
----------------------------------------------------------------------------------------------------
I've done this tutorial before, at the Workshop at Rice, but I've been having problems with the SW configuration on my computer.
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You need to look at the synthesis report (.srp) file for the core that actually caused the error - C:\safe\working\fpga_designs\warp_intro\synthesis\ppc405_0_wrapper_xst.srp in this case.
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Here's my <ppc405_0_wrapper_xst.srp> file:
--------------------------------------------------------
Release 9.1.02i - xst J.39
Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
-->
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input Format : MIXED
Input File Name : "ppc405_0_wrapper_xst.prj"
---- Target Parameters
Target Device : xc2vp70ff1517-6
Output File Name : "../implementation/ppc405_0_wrapper.ngc"
---- Source Options
Top Module Name : ppc405_0_wrapper
---- Target Options
Add IO Buffers : NO
---- General Options
Optimization Goal : speed
Optimization Effort : 1
Hierarchy Separator : /
---- Other Options
Cores Search Directories : {../implementation}
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/EDK91i/hw/XilinxProcessorIPLib/pcores/ppc405_v2_00_c/hdl/vhdl/ppc405_top.vhd" in Library ppc405_v2_00_c.
Entity <ppc405_top> compiled.
Entity <ppc405_top> (Architecture <structure>) compiled.
Compiling vhdl file "C:/safe/working/fpga_designs/warp_intro/hdl/ppc405_0_wrapper.vhd" in Library work.
Entity <ppc405_0_wrapper> compiled.
Entity <ppc405_0_wrapper> (Architecture <STRUCTURE>) compiled.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <ppc405_0_wrapper> in library <work> (architecture <STRUCTURE>).
Analyzing hierarchy for entity <ppc405_top> in library <ppc405_v2_00_c> (architecture <structure>) with generics.
C_DCR_RESYNC = 0
C_DETERMINISTIC_MULT = 0
C_DISABLE_OPERAND_FORWARDING = 1
C_DSOCM_DCR_BASEADDR = "0000100000"
C_DSOCM_DCR_HIGHADDR = "0000100011"
C_ISOCM_DCR_BASEADDR = "0000010000"
C_ISOCM_DCR_HIGHADDR = "0000010011"
C_MMU_ENABLE = 1
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <ppc405_0_wrapper> in library <work> (Architecture <STRUCTURE>).
Set user-defined property "X_CORE_INFO = ppc405_v2_00_c" for unit <ppc405_top>.
Entity <ppc405_0_wrapper> analyzed. Unit <ppc405_0_wrapper> generated.
Analyzing generic Entity <ppc405_top> in library <ppc405_v2_00_c> (Architecture <structure>).
C_DCR_RESYNC = 0
C_DETERMINISTIC_MULT = 0
C_DISABLE_OPERAND_FORWARDING = 1
C_DSOCM_DCR_BASEADDR = "0000100000"
C_DSOCM_DCR_HIGHADDR = "0000100011"
C_ISOCM_DCR_BASEADDR = "0000010000"
C_ISOCM_DCR_HIGHADDR = "0000010011"
C_MMU_ENABLE = 1
WARNING:Xst:2211 - "C:/EDK91i/hw/XilinxProcessorIPLib/pcores/ppc405_v2_00_c/hdl/vhdl/ppc405_top.vhd" line 508: Instantiating black box module <PPC405>.
Entity <ppc405_top> analyzed. Unit <ppc405_top> generated.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <ppc405_top>.
Related source file is "C:/EDK91i/hw/XilinxProcessorIPLib/pcores/ppc405_v2_00_c/hdl/vhdl/ppc405_top.vhd".
WARNING:Xst:647 - Input <PLBC405DCUSBUSYS> is never used.
WARNING:Xst:647 - Input <PLBC405DCUREARBITRATE> is never used.
WARNING:Xst:647 - Input <PLBC405DCUSERR> is never used.
WARNING:Xst:647 - Input <DCRCLK> is never used.
WARNING:Xst:647 - Input <PLBC405DCUWRBTERM> is never used.
WARNING:Xst:647 - Input <PLBC405DCURDWDADDR<0>> is never used.
WARNING:Xst:647 - Input <PLBC405ICUWRBTERM> is never used.
WARNING:Xst:647 - Input <PLBC405ICUWRDACK> is never used.
WARNING:Xst:647 - Input <PLBC405DCURDBTERM> is never used.
WARNING:Xst:647 - Input <PLBC405ICURDWDADDR<0>> is never used.
WARNING:Xst:647 - Input <PLBC405ICUREARBITRATE> is never used.
WARNING:Xst:647 - Input <PLBC405ICUSBUSYS> is never used.
WARNING:Xst:647 - Input <PLBC405ICUSSIZE<0>> is never used.
WARNING:Xst:647 - Input <PLBC405ICURDBTERM> is never used.
WARNING:Xst:647 - Input <PLBC405DCUSSIZE<0>> is never used.
WARNING:Xst:647 - Input <PLBC405ICUSERR> is never used.
Unit <ppc405_top> synthesized.
Synthesizing Unit <ppc405_0_wrapper>.
Related source file is "C:/safe/working/fpga_designs/warp_intro/hdl/ppc405_0_wrapper.vhd".
Unit <ppc405_0_wrapper> synthesized.
=========================================================================
HDL Synthesis Report
Found no macro
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Loading device for application Rf_Device from file '2vp70.nph' in environment C:\Xilinx91i;.
=========================================================================
Advanced HDL Synthesis Report
Found no macro
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
------------------------------------------
I can't make much sense of it. What does "Found no macro" mean?
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Is that the full .srp file? What you posted looks the same as the top part of the usual ppc405_0_wrapper_xst.srp, but is missing about 150 lines. You can look at the corresponding log file from one of the workshop exercises; look in the synthesis folder of any of the posted XPS projects. There is no error message in what you posted- if XST is dying on synthesizing the PPC405 wrapper, it must have printed something further down in the log.
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I did a clean install of my Xilinx SW tools and got Lab 1 to work! Well, as far as I can w/o the HW :-). I probably screwed up something trying to have both 9.2 and 9.1 on the same computer. Thanks for your help.
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