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In your Ref. Design OFDM_TxRx_MIMO core, where do the <dout> Xilinx Simulink blocks get their input? According to Help, they are shared memory From registers who share with To registers, but I cannot find the corresponding To registers. Specifically, the <dout> blocks under /OFDM Tx MIMO/Training_Data/Training_Pilots/Scrambled_Pilot_Inserter . Thanks.
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The Sysgen blockset includes two register blocks: To and From/To. After running a model through sysgen2opb/OPB Export, these blocks are replaced by memory mapped registers connected to an OPB slave interface. To registers are read-only (from the OPB perspective); From/To registers are read/write. For simulation, the read/write registers are assigned a value at initialization via the block's Initial Value parameter. In hardware, these registers are initialized by the C code writing values via the OPB.
The first lab exercise from our most recent workshop illustrates the use of these blocks in a much simpler model.
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