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hi,
In our lab, each Warp board has two radio cards, which are placed on No. 2 and No. 3 radio card interface. In the following illustration, I name the radio card on No.2 radio interface as radio card 2 and the radio card on No.3 radio interface as radio card 3. I am trying to test the receiving characteristics of the radio cards. The test procedure are listed as follows:
1. Generate the 10KHz sinesoid baseband signal by a signal generator. The signal is modulate by 2412MHz radio frequence.
2. Conneting the generated signal to both radio cards at the same board by using a splitter. Meanwhile I can monitor the signal from a Spectrum Analysis.
3. Set the two warp working at the same conditions. The radio initialization codes are described as below, and RxHp is closed:
//Set lowpass filter corner frequency on transmit
WarpRadio_v1_TxLpfCornFreqCoarseAdj( 0x1, FIRST_RADIO | SECOND_RADIO);
//Finally turn on the power amplifier
WarpRadio_v1_TxEnSoftControlEnable(FIRST_RADIO | SECOND_RADIO);
WarpRadio_v1_SoftwareTxGainControl(1, FIRST_RADIO | SECOND_RADIO);
WarpRadio_v1_24AmpEnable(FIRST_RADIO | SECOND_RADIO);
WarpRadio_v1_SetTxTiming(FIRST_RADIO, 50, 0, 0, 0);
WarpRadio_v1_SetTxTiming(SECOND_RADIO, 50, 255, 0, 0);
WarpRadio_v1_SetTxGainTiming(FIRST_RADIO | SECOND_RADIO, 0x3F, 0xF, 2);
WarpRadio_v1_BaseBandTxGain(0x0, FIRST_RADIO | SECOND_RADIO);
//**** End Radio Transmitter Initialization ****
//**** Begin Radio Receiver Initialization ****
//Enable AGC control of receive gains
/* Use these functions to override AGC in software */
WarpRadio_v1_RxEnSoftControlEnable(FIRST_RADIO | SECOND_RADIO);
WarpRadio_v1_SoftwareRxGainControl(1, FIRST_RADIO | SECOND_RADIO);
WarpRadio_v1_RxLNAGainControl(0x2,FIRST_RADIO | SECOND_RADIO);
WarpRadio_v1_RxVGAGainControl(0x10,FIRST_RADIO | SECOND_RADIO);
WarpRadio_v1_RxLpfCornFreqCoarseAdj(0x1, FIRST_RADIO | SECOND_RADIO);
//**** End Radio Receiver Initialization ****
4. Monitor the received I,Q signals of the two radio cards on chipscope.
After checking the I,Q signals on chipscope, I found out there is some jitter noise on both I,Q of radio card 3. The power of jitter noise is much larger than the signal's power. For example, the amplitude of the jitter noise can be 0.5 when the signal's is only 0.2. Meanwhile the I,Q signals of radio card 2 are good. And I try another warp board in our lab, the same thing happens.
Can you help me to figure out whether there are problems in the radio cards' initialization codes. Otherwise this problem may be caused by the digital interface of the radio card 3. And what should I do if I want to switch the radio card from the No. 3 interface to the other interfaces, such as No. 1 or No. 4.
Best regards,
jlliu
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Your initialization code looks fine (I'm assuming you called WarpRadio_v1_reset() somewhere above this).
My first guess as the source of different results between slots 2 and 3 would be timing issues. Are you using the latest version of the radio_bridge pcore (currently 1.08, svn rev 596)? How did you construct the EDK project- base system builder, or by hand? If by hand, it's worth double checking constraints for the ADC data signals. You should also double check the sampling clock connections- the twisted white/green cables running from the clock board to each radio. The polarity of these cables is important; switching one would cause the ADCs to sample out-of-phase, potentially introducing setup/hold issues on just one radio.
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For initialization, your assumption is right. I have the reset code as below at the beginning of initialization.
WarpRadio_v1_Reset((unsigned int *)XPAR_RADIO_CONTROLLER_0_BASEADDR);
The radio_bridge version of mine is 1.08a. I built up the EDK project by system builder and changed the CLK connection by hand. How can I check the constraints for the ADC data signals?
I think the connection of the twisted white/green cables is correct. For I have switched the radio card 2 and radio card 3. At the radio interface 2, radio card 2 works well. But at radio interface 3, it does not.
Based on your suggestion, the problem may be caused by the problem of handy CLK connection during the EDK project's setup or the digital interface between the radio card 3 and the baseband.
Thanks a lot,
jlliu
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If you've been moving boards between daughtercard slots (something we suggest you avoid doing), I would strongly recommend double checking the clock connections. The radio board has the polarity of its clock inputs marked (GND - + GND); for the clock board, refer to the users guide.
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I solved the problem by adding converter_clock_in = sys_clk_OPB for the radio bridge of radio card 3 in the mhs file. After building up the project by system builder, we still need to do some handwork, such as clock connection for some pcores.
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