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In the Simulink model of transmitter, there are several references to the IFFT x_n output running three cycles ahead of the input data, i.e. by the time IFFT starts processing the first data sample, the x_n provided to the Training_Data block is already at 3. Is there a way to change this value (in case we introduce additional processing delay between the packet buffer and the IFFT) ?
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No; you'll have to build a new control system that delays the start of the FFT by however many extra cycles your processing requires.
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Thanks for the quick response. Does delaying the IFFT start really solve this problem with the current setup? My impression is that the delayed IFFT start will only delay the x_n output (which is fed back to pkt buffer) accordingly. We were thinking of disconnecting the x_n output and generating our own x_n (advanced in time to compensate for the additional delay between input data and IFFT). Does that make sense?
Thanks.
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That's what I meant- that you would have to ignore the FFT core's x_n output and create a control system that produces the sample index your modulator/Tx processing requires.
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Thanks for the clarification.
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