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Hi, I tried to download SREC data to spi flash. It fails due following error. CPLD holds configuration provided by warpproject and left-most switch in the configuration DIP switch is set to 1.
Secondly If I use xps_spi core with different cpld configuration (connections from xps_spi to flash), would SREC bootloader be able to access the SREC Image, post flash writing?
Boundary-scan chain validated successfully.
1: Device Temperature: Current Reading: 33.15 C, Min. Reading: 28.72 C, Max. Reading: 33.64 C
1: VCCINT Supply: Current Reading: 0.993 V, Min. Reading: 0.993 V, Max. Reading: 0.996 V
1: VCCAUX Supply: Current Reading: 2.502 V, Min. Reading: 2.496 V, Max. Reading: 2.505 V
'1': SPI access core not detected. SPI access core will be downloaded to the device to enable operations.
INFO:iMPACT - Downloading core file /opt/Xilinx/14.4/ISE_DS/ISE/virtex6/data/xc6vlx240t_spi.cor.
'1': Downloading core...
Match_cycle = NoWait.
Match cycle: NoWait
LCK_cycle = NoWait.
LCK cycle: NoWait
done.
INFO:iMPACT:2219 - Status register values:
INFO:iMPACT - 0011 1111 1001 1110 0000 1011 1000 0000
INFO:iMPACT:2492 - '1': Completed downloading core to device.
'1': IDCODE is '202018' (in hex).
'1': ID Check passed.
'1': IDCODE is '202018' (in hex).
'1': ID Check passed.
'1': Erasing Device.
'1': Using Sector Erase.
'1': Programming Flash.
'1':Programming in x1 mode.
'1': Configuration data download to FPGA was not successful. DONE did not go high, please check your configuration setup and mode settings.
INFO:iMPACT - '1': Flash was not programmed successfully.
PROGRESS_END - End Operation.
Elapsed time = 376 sec.
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I haven't used the SPI Flash in a while - I'm guessing you've already read the SPI flash config howto? What SPI PROM device model did you select in iMPACT?
I'll be back in the office this week and will re-test the howto instructions with iMPACT 14.4.
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I have already read SPI Config howto, The only difference is I am trying to download SREC Linux kernel image. I hope this doesn't make any difference. I am using M25P128, with N25P128 it doesnt detect flash.
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My kernel.srec image is 9.4Mb so i am generating mcs file as follows. Previously I was using wrong size. But the following mcs file also fails. It generates 26Mb kernel.mcs file.
promgen -spi -p mcs -c FF -s 16384 -data_file up 0 kernel.srec -o kernel.mcs
If i use gui method to generate mcs file it needs atleast one download bit file. In my case, 8.8 Mb is the size of download.bit and total of 18.2 data doesn't fit in flash. Please reply if you get any clue about it.
Last edited by ss (2015-Jan-05 09:58:36)
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Ah, I misunderstood your application. I have only used the SPI flash to hold FPGA config bitstreams. The iMPACT tool for writing data to the SPI flash assumes you're writing a valid configuration bitstream. It's not surprising you see an error when writing other data formats. Have you created an FPGA design which can read the SPI flash (and modified the CPLD design accordingly)? I would be curious if your design sees the expected data in the SPI flash. I suspect iMPACT is writing the flash, then detects the error condition post-write.
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Hi, Yes I got it, configuration file is must whether I use promgen or impact. I am using SREC bootloader to load kernel into RAM. Kernel srec file is 9.4Mb..
Now, i can only add data file after a configuration file. Can you suggest any method to generate valid configuration file below 8.8Mb, So that both configuration file and kernel srec file fit into flash?
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The FPGA bitstream size is fixed - for the V6LX240T the .bit file is always 9.2MB.
Have you considered using the SD card? You can modify the CPLD to connect FPGA pins to the SD card SPI pins.
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Hi, as last option i may change srec bootloader code to load it from sd card. i just wanted to have a quick solution.
I would like to ask one more thing, if i use xps_spi to interface flash memory it doesn't show that in generated linker script option. secondly, uboot_bsp gives error if i select xps_spi for flash memory. also if i have spi connections to flash via cpld (from xps_spi to flash) srec bootloader doesn't read flash correctly (configuration file was there but all it read was 000.. ).. do you have any clue if xps_spi core is correct way to interface flash? or are there any special settings.. I have seen designs that axi_quad_spi core works with standard spi settings..
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Sorry I can't be more help- I have never tried interfacing to the SPI flash using the Xilinx SPI core. I have used the Xilinx axi_spi core to read/write from the SD card from the MicroBlaze. This required a custom CPLD design to bridge the SD card pins to FPGA I/O. I think a similar design should work for read/write to the SPI flash.
I would like to ask one more thing, if i use xps_spi to interface flash memory it doesn't show that in generated linker script option.
I think that's right- the SPI flash won't be directly addressable from the MicroBlaze bus interfaces. The SPI core has memory-mapped registers which facilitate read/write of arbitrary offsets in the SPI flash. I don't know whether the SPI core driver or corresponding Linux driver can map the SPI flash to a virtual address.
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