WARP Project Forums - Wireless Open-Access Research Platform

That WARPLab example constructs a waveform from a standard preamble (for AGC) followed by a simple sinusoid. There is no modulation schemed involved. The WARPLab reference design moves raw waveforms between MATLAB and the WARP hardware. You can construct any waveform you like in your m code, then test the waveform via the RF interfaces on the WARP hardware. The hardware itself does not implement any modulation scheme.

How much is the data shifted?  My guess is that you are seeing the manifestation of the "agc_trig_delay" (see line 38 of wl_example_siso_txrx).

You can see the FPGA architecture to understand the hardware that is running inside the FPGA.  In terms of the software that is running on the Microblaze, I would start with wl_node.c and then branch out to other files.  In terms of sample processing, a lot of low level interaction with the hardware occurs in the custom Sysgen cores like the warplab_buffers core.   Depending on how much embedded programming experience you have, it might be better to leave the WARPLab hardware / software as-is and then interact with the hardware at the sample level via Matlab.

You need to clearly explain the experiment you are running, what you are expecting to see, and what you are actually seeing.

1. What do you mean by a "data shift"? This term is very vague.

2. What do you mean by a "notch in the center?" Again, this is vague and does not mean anything to me without further clarification.

girish wrote:

I want to want know is tx and rx of WARP V2 are phase locked when I am using SISO on same board

The phase relationship or a transmitting radio and a receiving radio is fixed when they are sharing a common clock. This is the case when you are using a single board.

Is baseband clock is Synchronized  for Transmitter and Receiver?

Yes- all RF interfaces on the same node share sampling and RF reference clocks.

Kindly  provide me your mail-id so that I send you files

You can post images of your graphs on a public server or service like Dropbox then share the URLs here.

In the WARPLab reference design the RSSI ADC is clocked at 10MHz. The I/Q converters (Tx DAC and Rx ADC) are clocked at 40MHz. The 10MHz and 40MHz clocks are synchronous, both derived from the 80MHz TCXO on the WARP v3 board.

Parameter of transmitted signal: BW= 10 MHz, LTE Signal, Sampling rate=40 MHz.  Channel : Shorted between TX and RX
I used manual gain control.

The input data and the output spectrum is plotted and attached.
There is notch at the center at the output.
I want to know why its coming and how can I remove it?

First, you must have >30dB attenuation when connecting Tx to Rx via a cable. A full-power Tx signal can damage the Rx circuits.

The notch at DC is normal, caused by the high-pass filter in the MAX2829 Rx path. Direct-conversion transceivers (like the MAX2829) typically require zero DC component in Tx signals and block DC in the Rx signal to avoid feed through of the RF carrier signal.

Is this hold true for WARP v2?

Yes- in WARPLab on WARP v1/v2 hardware the RSSI ADC is clocked at 10MHz, synchronous with the Tx and Rx ADCs, which are both clocked at 40MHz. The source clock is the 40MHz TCXO on the Clock Board.