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I have been poring over the details of WARPLAB over the last couple of days and had a few questions. First off, thanks for some really good documentation this time. I needed to know how the 'download.bit' file is generated in this case. Is the design procedure the same as that of the transmitter (or the adder)? If so, then please clarify on what IO interfaces should we select during the initial BSB setup.
Thanks in advance.
Sincerely,
Kshitij
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The flow is nearly identical to the normal sysgen2opb flow. The best example of the flow is the sweeping transmitter (lab 2 from the latest workshop).
The full XPS project for SISO WARPLab is available here: http://warp.rice.edu/bigFiles/WARPLab_siso_xps.zip.
There are a few details that differ from the workshop lab:
-In the Sysgen core, you have to modify the model after running sysgen2opb but before exporting the pcore. There is an adder that needs to be placed between the Rx dual-port block RAM read address port and the address signal. This adder is used to implement the circular buffer in the WARPLab receiver. Look at the file '/pcores/warplab_siso_opbw/mdlsrc/warplab_siso.mdl' in the XPS project to see this.
-In the lab, only the two DAC signals are routed from the custom core to the radio bridge. For WARPLab, you need to hook up additional radio signals: ADC_I, ADC_Q, ADC_I_OTR, ADC_Q_OTR, RSSI_D, RSSI_CLK.
-Two signals from the sysgen core (debug_capturing and debug_transmitting) are routed to top-level ports, connected to digital I/O on the FPGA board. These signals are used for observing and debugging things in hardware.
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Thanks ... will get to work on it.
Regards,
Kshitij
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