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#1 2008-Mar-06 02:56:03

DQ A
Member
Registered: 2007-Aug-22
Posts: 44

Shared BRAM and ofdm_timer and others

I have multiple questions here.

1) The shared BRAM between OFDM core and PPC should be able to hold multiple received and transmitted packets. Does the OFDM core know how to handle this situation? If not, it still should be easy to deal with multiple transmitted packets in MAC layer by managing the buffer ourself. But I am concerned about receiving packets. If interrupts are disabled, we may stop the processing of incoming packets. Will the ofdm core know to put later packets in the continuous buffer? Please point me to some sample design if you have.

2) In the OFDM reference design, you initiated one ofdm_timer. Can we add more if we need it? How do we connect it to the intc? I am also wonder if the PPC system has a timer for us to use.

3) Some header files are not present in the SVN repository, but are included in the reference design, such as pktDetector, ofdm_Timer, txrx_mimo. Did I miss something?

4) I found in the file "ofdm_txrx_mimo.h", the register definitions are different than what's in the documentation at http://warp.rice.edu/trac/wiki/OFDM/MIM … Registers. Should we be concerned about it?

Also in the same header file, we have the following:
#define ofdm_txrx_mimo_SMWO_PktBufferBER_OFFSET (OFDM_TXRX_MIMO_OFFSET+0x10000)
#define ofdm_txrx_mimo_SMWO_RxModulation_OFFSET (OFDM_TXRX_MIMO_OFFSET+0x20000)
#define ofdm_txrx_mimo_SMWO_TxModulation_OFFSET (OFDM_TXRX_MIMO_OFFSET+0x30000)

Are these memory or registers?
Thanks,

Last edited by DQ A (2008-Mar-06 02:57:36)

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#2 2008-Mar-06 03:41:11

murphpo
Administrator
From: Mango Communications
Registered: 2006-Jul-03
Posts: 5159

Re: Shared BRAM and ofdm_timer and others

1) The packet buffer is 128KB (a minimum-sized PLB BRAM), all of which is available to both the PHY and PLB. The PHY views this 128KB as 64 2KB buffers. There is a register in the PHY that defines which sub-buffer is used for Tx and Rx. The user code (WARPPHY/WARPMAC in the reference design) must manage the buffer assignments.

2) There is a Xilinx-provided opb_timer pcore. We designed the ofdm_timer in order to have a timer tied to the RSSI signal. The ofdm_timer pauses its backoff timer whenever the medium is busy, and does not interrupt the PowerPC to do so. This allows very easy carrier sensing without any per-medium-event overhead. If you need general-purpose timers, you should instantiate multiple opb_timer cores.

3) Those header files are generated by sysgen2opb. Since the source models are in svn, we leave the auto-generated header files out.

4) I still need to update the register map in the wiki; as noted on the page, it reflects the map from the previous version of the model. The changes weren't major; WARPPHY already uses the new map in the latest reference design.

The ofdm...SMWO...OFFSET parameters refer to shared memory blocks in the OFDM model. Read more about sysgen's shared memory extension on its page.

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