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We wish to only modify your ofdm_txrx_mimo model, but still have it integrated with the rest of the v8 Ref Design to work in HW.
1. When I convert your ofdm_txrx_mimo model into a core using sysgen2opb, the resulting model file is only 21.5MB, whereas your file is 32.8MB. What's the difference?
2. Should the "FPGA clock period" in the Sys Gen dialog box be 10ns? Does the "Target Directory" matter?
3. Besides connecting the modified core to the OPB bus, do we have to do anything else before generating addresses in XPS? We have disconnected your core, deleted its instance, and connected our core.
Thanks for your help.
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1) I wouldn't worry too much about the file sizes; these seem to vary with different versions of Sysgen and Simulink.
2) The clock period in the Sysgen token is not used for the EDK export flow; it's only used by the Sysgen compilation targets that generate full FPGA designs, not just cores that are integrated into larger systems. The timing constraints & analysis are handled by the EDK in this case.
3) sysgen2opb only generates a simple MPD file for the core. You will need to modify this file to include specifications for the PLB BRAM interface and interrupt lines. This was discussed in a previous thread. You can refer to the MPD included with the ofdm_txrx_core in the reference design for the specifics.
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