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#1 2015-Jul-17 12:48:22

crimechb
Member
Registered: 2010-Sep-01
Posts: 205

About DLL clock

Dear Sir,

We follow below link to change the rx and agc model and AD9512 and AD9963.
http://warpproject.org/forums/viewtopic.php?id=2754

We would like to adjust DLL clock and set up the ADC/DAC sampling rate to 20Mhz.

But we feel confused about our test case.

Case 1: STA can not access AP.

Code:

RefClk=40M,M=4, N=8, DLL_DIV=1
REFCLK*M=40M*4=160M (100~310)
DLL_CLK=REFCLK*M/(N*DLL_DIV)=40M*4/(8*1)=20M

Case 2: STA can access AP.

Code:

RefClk=20M,M=1, N=2, DLL_DIV=1
REFCLK*M=20M*1=20M (not 100~310)
DLL_CLK=REFCLK*M/(N*DLL_DIV)=20/(2*1)=10M

How to adjust the M&N value and set up the ADC/DAC sampling rate to 20Mhz.
Could you provide us an example ?
Another question : If the ADC and DAC sampling rate are different .Does the STA still can access AP?

Thanks,

Last edited by crimechb (2015-Jul-17 12:48:53)

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#2 2015-Jul-19 22:53:57

murphpo
Administrator
From: Mango Communications
Registered: 2006-Jul-03
Posts: 5159

Re: About DLL clock

Is there a particular reason you're trying to use the AD9963 DLL? The easiest way to achieve a 20MHz sampling frequency is to bypass the DLL and feed a 20MHz refclk directly. You can use the AD9512 dividers for this.

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#3 2015-Jul-20 04:36:16

crimechb
Member
Registered: 2010-Sep-01
Posts: 205

Re: About DLL clock

Dear murphpo,

We would like to use special clock . ex:16Mhz..
So we try to modify the DLL clock .

We have solved previously test case problem. We must to set right M value.
* DLL_M DLL multiplication (M) parameter; must be in [0,1,...,31] for multiplications of [1,2,...,32]

Now we have another question. When I modify DLL_DIV. only DLL_DIV=1 work. Other value does not work.(2&4)
Do I need to set other parameter?

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#4 2015-Jul-20 23:14:38

murphpo
Administrator
From: Mango Communications
Registered: 2006-Jul-03
Posts: 5159

Re: About DLL clock

I have never used the DLL in the AD9963 (all our designs have relied on the dividers in the AD9512), so I'm not positive about this issue.

Looking at the datasheet, the DLLDIV parameter only affects the EXTDLLCLK signal. This signal does not drive the ADCs or DACs- it can only drive the TRXCLK or TXCLK pins, which are tied to the FPGA. Have you modified the AD9963 config to select the EXTDLLCLK signal as the TRXCLK output?

If not, can you describe your exact configuration in more detail?

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#5 2015-Jul-21 03:29:18

dinolai
Member
Registered: 2015-Jul-21
Posts: 3

Re: About DLL clock

Dear murphpo,
We try to use DLL_DIV to change the clock. Now we have some questions :

we follow the formula : DLL output clock = REFCLK*M/(N*DLL_DIV). 

1. If we set the RefClk=40M , DLL_M=2 , DLL_N=4 , DLL_DIV=1 it can work( STA can access AP ) , as shown below
https://www.dropbox.com/s/rcqoafbli7e2g0j/1.png?dl=0
2. But we set the RefClk=40M , DLL_M=2 , DLL_N=2 , DLL_DIV=2 it can not work( STA can not access AP ) , as shown below
https://www.dropbox.com/s/hqbagmb9nu0zsxb/2.png?dl=0
We have tried to let the AD_DACCLKSRC_DLL  -->  AD_DACCLKSRC_EXT  , the STA still can not access AP
3. If the DLL_DIV=1, it can work successfully. We can change the RefClk , DLL_M , DLL_N to get the clock which we want to use.
We follow the data sheet of AD9963 :
00: DLL output is directly driven out. Divider is bypassed.
01: DLL output is directly driven out. Divider is bypassed.
10: DLL output is divided by 2.
11: DLL output is divided by 4
If I let DLL_DIV=2 or 3, it always can not work( STA can not access AP ). Do you know why?

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#6 2015-Jul-21 10:48:30

murphpo
Administrator
From: Mango Communications
Registered: 2006-Jul-03
Posts: 5159

Re: About DLL clock

Per Figure 65 in the AD9963 datasheet, the DLLDIV parameter only affects the EXTDLLCLK signal. This signal can only be routed to the TRXCLK or TXCLK pins. It does not affect the DLLCLK which drives the ADCs and DACs. The TRXCLK signal is used by the FPGA to capture the ADC outputs on the TRXD bus. You must configure the TRXCLK output to provide a clock which the w3_ad_bridge core can use to capture the TRXD signals. If your change the DLLDIV parameter, such that the TRXCLK signal runs at a different frequency from the TRXD signals, the FPGA will not capture valid I/Q samples.

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