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hi,
I am debug the ethernet RX high MAC rencently,but i am confused about the process about the data flow from the Ethernet port to ddr3 .can anyone help me ?
thank you!!
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The 802.11 ref design uses the axi_ethernet core as the Ethernet MAC and an axi_dma core to move packets between the MAC and memory.
The axi_dma core is configured at boot to handle Ethernet receptions. Every time an Ethernet packet is received the axi_dma moves the received bytes to a pre-allocated buffer in DRAM. The axi_dma then asserts its interrupt. The C code implements the interrupt service routine. The ISR examines the received packet. For packets which should be transmitted via the wireless interface, the packet is encapsulated and stored in one of the Tx queues. For Ethernet packets which will not be transmitted over the air, the ISR discards the received packet. At the end of the axi_dma ISR the DRAM buffers are cleared and re-submitted to the axi_dma hardware. The axi_dma hardware is then ready to handle new Ethernet receptions.
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when the ethernet port start to recive the ehernet data,and when the DMA is start to transmit data.
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I'm not quite sure I understand the question. You can find the data sheet for the Ethernet peripheral here. Also, you can find the data sheet for the Ethernet DMA here.
In general, the Ethernet peripheral receives starts to receive bits from the packet when it is presented on the Ethernet port. The Ethernet peripheral has an internal buffer that will buffer the packet and when the packet is complete, it will transfer the data to the DMA so that the DMA can send the data to where it needs to go in the system.
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I am not sure whether I understand DMA correctly?The ethernet data from ehernet port will be buffered until the packet is complte.and then the DMA interrupt will be triggered,submit the packet to DDR3 by use of DMA?
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The Ethernet PHY (the Marvell chip near the Ethernet connectors) buffers incoming data until the checksum can be verified. If the checksum passes the PHY transfers the packet to the Ethernet MAC (in the FPGA). The Ethernet MAC streams incoming packets to the axi_dma core. The axi_dma is pre-configured to transfer all Ethernet receptions to DRAM. The axi_dma core asserts its interrupt output after it has transferred a packet to DRAM. The C code responds to the interrupt, analyzes the packet in DRAM and proceeds from there.
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I am confused about the relationship between Buffer descriptor and DMA core.with the arriaval of ethernet data ,both of them were controlled by the hardware?
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A buffer descriptor ("BD" in the axi_dma driver) is a data structure in the C code which is used to configure the axi_dma core. For Ethernet receptions a buffer descriptor specifies the address and size of a memory location where the axi_dma core should store a received packet. The application allocates memory and creates new BDs at boot. The BDs are submitted to the axi_dma core. The axi_dma core consumes one BD for each Ethernet reception. The interrupt service routine retrieves the list of used BDs from the axi_dma hardware after the Rx interrupt asserts. When the ISR is finished it re-submits the processed BDs back to the axi_dma core for use by future receptions.
I would strongly encourage you to read the documents Erik linked to above. You should also review the axi_dma and axi_ethernet application examples provided by Xilinx. These examples are in your Xilinx installation directory:
/Xilinx/14.4/ISE_DS/EDK/sw/XilinxProcessorIPLib/drivers/
-axidma_v7_01_a/
-axiethernet_v3_00_a/
Our axi_dma/axi_ethernet code in wlan_mac_high_framework is based on these examples.
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