WARP Project Forums - Wireless Open-Access Research Platform

We only got access to the 10.1 tools a few weeks ago. We're working on an OFDM reference design for these tools; it will probably be a few weeks before it's ready. Xilinx changed a lot of stuff in this version- everything from PLB support in Sysgen to no more OPB in the EDK. The next reference design will take advantage of most of these improvements (and will work around a few new problems).

I'm aiming to have it posted by mid-May. I think we've already figured out how to handle all of the changes in the tool flows, so it's just a matter of porting each of the constituent designs.

In the next ref design, I expect the PHY processing logic will remain the same; just the processor interface will change. The PLB support in Sysgen 10.1 is usable, but has some quirks that we're still trying to work around. For example, it seems the tools can't generate a register that is both readable and writable (from the perspective of the host processor). Our current OPB flow allows this, and we use it extensively.

I apologize it's taking longer than I'd guessed. We've converted all of the PHY cores and successfully exported them using 10.1's PLB export. We've also built a full EDK project integrating the cores and tested it over the air. The last missing piece is Ethernet. The new Ethernet MAC doesn't include DMA support; the EMAC choices are xps_ethernetlite (no DMA) or xps_temac (DMA only when used with the MPMC). Our only alternative is to use the xps_centraldma core instead, which requires more code changes than we'd hoped. We hope to have a full reference design working in the next few weeks...

We will still use the BRAM interface for the PHY's packet buffer.

I posted a snapshot of the current design to OFDM_ReferenceDesign_v10_v05.tar.gz.

This is very much a work in progress - it is not a stable, fully functional reference design (yet).

What's missing:
-The DMA core is not yet integrated, nor are the C code changes required to use it.
-In its current form, the design doesn't actually move packets in/out of the PHY (can't, without DMA).

What's there:
-I've verified it receives packets transmitted by a node using ref design v08.
-The PLB46 versions of our PHY cores are all included, exported via Xilinx's PLB export flow in Sysgen 10.1. The updated Sysgen models are already in the repository.
-The overall bus architecture is there:
   PowerPC
      - PLB46 (64-bit 80MHz)
         - Xilinx & non-PHY WARP cores
         - PLB46_PLB46_Bridge
            - PLB46 (32-bit 40MHz)
               - OFDM cores

Hi,

I am getting the following error when trying to compile the above sysgen model in MATLAB 2007b and Sysgen10.1:

"Error reported by S-function 'sysgen' in 'ofdm_txrx_mimo/OFDM Rx MIMO/FFT & Chan Est/FFT/FFTx':
An internal error occurred in the Xilinx Blockset Library."

Is this error because of the difference in MATLAB version? We are using 2007b and all Xilinx v10.1 tools.

Regards
Atanu

Thanks, with 2007a, the PHY model is running in sysgen 10.1.1. We are building our PHY model based on your sysgen model. However, we are not upto the PLB export stage. As you have mentioned, we also hope that by the time we reach to this stage (another 2 months), Xilinx releases 10.1 stable version.

I'm not sure what the compilation problems are, but coincidentally we have made a new version of the version 10 beta reference design and have posted it  here. We've copied over all of the necessary peripherals to the local project, so it should be portable.

Just a brief update on what has changed:
- We've figured out the Ethernet MAC situation (using a central dma controller)
- With the exception of the EEPROM core that we are still porting over, the hardware in this beta is exactly like it will be in the official release.
- The code for the MAC behavior and underlying WARPMAC/WARPPHY frameworks will change dramatically between now and the reference design 10 release. The code had been cobbled together through many fundamental architecture changes. It's time we clean house.

I believe that every core in the new ref design is included with the EDK (i.e. none must be purchased separately). Our PHY cores are still designed in System Generator; the source models are in the repository, but you'll need a license for System Generator to edit them.

We tried using the download.bit that comes with the reference design 10 beta (version 14) linked above. But we haven't been able to get it to work. The initialization messages on the terminal seem all right. Each WARP board can ping itself (so Ethernet must be working) but not the other. Reference design 9 is working just fine. Does anything need to be done before running version 10 of the ref design?

We're not able to get the release v10 version to work either. Each node can ping itself but not the other. The initialization messages seem all right. Reference design v9 works fine though. In both cases we are using the download.bit that comes with the reference design. (Rebuilding with 10.1.02 tools gives the same results.) Any idea how we could fix this?

Thanks, that seems to have been the problem. (Incidentally, we were using radio 2 in SISO mode.) The v11 beta works well.