You are not logged in.
We measured a clock drift of 1.36 ppm between two boards. We have software clocks that use the 64-bit timebase as a time reference. Do you know what is the maximum clock/frequency drift reported by the manufacturer for the oscillator (internal CPU clock?) that is incrementing this timebase?
I was going through the datasheets for Virtex-II and PPC but could not find this information.
Thanks
Offline
The FPGA has no internal oscillator. Every synchronous element in the chip is run by a clock signal derived from an external oscillator. The frequency tolerance of this oscillator will determine the range of frequency offsets you observe between boards. On your kits, the design uses a 100MHz oscillator (Y5, on the back of the board); 1.36ppm is well within the tolerance of this part.
Offline