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Hi,
I am trying to understand the soft demap block. For the 16 QAM every IQ sample represents 4 bits right therefore I was assuming that there would be 2 sets of LLR A and LLR B at the output , however from the timing diagram I see that for 48 clock cycles of IQ valid we get 24 valid clock cycles of LLR A and LLR B . How is that possible ?
Can you please explain? or guide me to a reference for this?
Thanks
Sadia
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I'm not sure where you're seeing only 24 LLR A/B pairs for a 16-QAM demod. Are you looking at the first OFDM symbol (the SIGNAL field)? That is always transmitted at 6Mbps (BPSK 1/2 rate code), containing 24 data bits.
Each LLR value represents one coded bit. When the code rate is >1/2 (i.e. puncutred) the Rx pipeline inserts additional LLR values after the demod, representing zero-confidence values for the punctured coded bits. Each LLR A/B pair at the input to the decoder represents 1 data bit. Each LLR A/B pair is loaded into the decoder in one cycle. For example, with the 24Mbps rate (16QAM 1/2 rate code) there are 96 data bits per OFDM symbol. The "LLR Valid" signal at the decoder input is asserted for 96 cycles per OFDM symbol.
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