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When two boards share the same reference clock (input to the MAX2829 chip), I noticed a previous post:
"There will be an inter-radio phase offset that changes with every reset of the radios' PLLs (due to reset, re-tuning or power cycling)."
The PLLs in question are the frequency synthesizer in the MAX2829, correct?
As I understand PLL frequency synthesizers, however, the feedback loop in the PLL makes the output phase locked to the input. The output frequency is a factor of the input frequency so phase synchronization here means that the rising edge of the input locks to one of the rising edges of the output, and this happens every N (freq. Ratio) cycles.
Wouldn't this mean the phase offset remains constant even after a reset? Experimentally I know this is not the case but am wondering why not.
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The PLL seeks to minimize the phase/frequency difference between the reference clock and a divided copy of the VCO output. This divider introduces the phase ambiguity. For a fractional-N PLL (like the MAX2829 PLL) the number of possible phase offsets is huge. Some PLLs (like the ADF4350) have the ability to reset the divider after the PLL has locked to establish a deterministic phase relationship between the reference and VCO. The MAX2829 PLL does not implement this feature. The MAX2829 does implement a "MIMO Mode", which keeps the PLL running even when the radio is in standby. This preserves the reference/VCO phase relationship across Tx/Rx state changes. Our reference designs enable "MIMO Mode" by default.
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