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By investigating the models existing in WARP repository, it seems to me that packet detection is power based -- detect the power boost from RSSI. Packet detection triggers AGC. The PHY processing is thus split into three pcores -- packet detection; AGC; and Rx baseband processing.
The performance for power based frame detection is fine in medium to high SNR. However, in low SNR or interference-limited environment (low SINR), we cannot only rely on power based packet dection. Our Rx packet detection is designed for this scenario. It mainly relies on correlation/coherent combining in digital domain to detect the existence of a packet. Note that correlation for this purpose does not need too much bit resolution. In between packets, the AGC should adjust the gain such that noise (or interference) power are kept in a sweet spot within the ADC range. Thus, when a packet comes, there is enough bits for correlation without change the gain, however, the clipping is also minimum or statistically acceptable. (If the incoming signal power is too high --- sorry buddy, back off your power please, you are interfering other users!)
After the detection of a packet, AGC will settle and lock to the best value for that packet until finishing the processing. For example in the preamble of 802.11a, we use the full 10 repetitions for simultaneous power estimation, frame detection and coarse frequency offset estimation. The first half of the gap between short preamble and long preamble are reserved for AGC settling.
It seems that we have to change the AGC pcore design. In the following are a few initial problems:
(A) AGC control pcore not only connects to OPB bus, but also connects to FPGA pins. It can seen that, in 'agc_rssi_threshd_det.mdl', there are gateway blocks that serve for this purpose. So, in general, what are the steps to develop a sysgen model include connections with off-chip components? I assume the names for these gateway blocks are special, so where can we find the list of names we can use?
(B) What is the VGC settling time for both coarse gain and fine_grained gain?
(C) The settling time for increasing gain and decreaing gain are same or different?
Please note that, in question (B) and (C), I am asking VGC. Since the time also depends on the FPGA logic, I would like to exclude time for this now. Just want to check your experience on VGC settling for both coarse gain and fine grained gain.
Thanks.
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zrcao wrote:
By investigating the models existing in WARP repository, it seems to me that packet detection is power based -- detect the power boost from RSSI. Packet detection triggers AGC. The PHY processing is thus split into three pcores -- packet detection; AGC; and Rx baseband processing.
This split is motivated by two things. First, the OFDM core itself is radio agnostic. It requires only digital I/Q signals sampled at 1/4 the system clock. No other radio control signals are required or produced by the transceiver. The AGC and packet detection cores are both tailored to the MAX2829 transceiver. Like you noted, the packet detector requires the RSSI signal from the radio. Likewise, the AGC core controls the MAX2829's gain interfaces. The packet detector and AGC cores are split for NDA reasons. The detector is our own design and is publically available. The AGC core is a custom implementation of a Maxim AGC algorithm; as a result, we can distribute the netlist for the core but not its source model.
The packet detection operation is actually split between the RSSI packet detection core and the OFDM receiver. The OFDM core has a cross-correlator which looks for the long training symbol in the packet preamble. This correlation must succeed before a packet is processed by the rest of the receiver. We think of it as course packet detection (i.e. energy thresholding based on RSSI, before AGC) and fine packet detection (i.e. post-AGC digital correlation).
zrcao wrote:
The performance for power based frame detection is fine in medium to high SNR. However, in low SNR or interference-limited environment (low SINR), we cannot only rely on power based packet dection.
We've found that our RSSI packet detector works well except in the lowest SNR cases (i.e. when the transmitting node is near the edge of our useable range). There's probably room for improvement in these cases.
zrcao wrote:
(If the incoming signal power is too high --- sorry buddy, back off your power please, you are interfering other users!)
This is exactly the scenario we desgined for. There is no back-channel communication in a random-access network, so nodes cannot make assumptions about where the next packet will come from, nor can they request adjustments of remote Tx power in real-time. As a result, after receiving a packet, the AGC immediately resets the amplifiers to near-maximum levels, in case the next packet comes from a distant node. If instead a packet arrives from a nearby node, the analog circuits in the RF transceiver saturate, producing a signal at the ADC which we've found lacks sufficient structure for meaningful digital correlation. The energy-based packet detector is still successful in this situation, given that the RSSI signal is useful over the full range of Rx power levels. The packet detection is then confirmed post-AGC using the long training symbol correlation in the OFDM receiver.
zrcao wrote:
(A) AGC control pcore not only connects to OPB bus, but also connects to FPGA pins. It can seen that, in 'agc_rssi_threshd_det.mdl', there are gateway blocks that serve for this purpose. So, in general, what are the steps to develop a sysgen model include connections with off-chip components? I assume the names for these gateway blocks are special, so where can we find the list of names we can use?
Any gateways in a System Generator model become top-level ports in the generated HDL. You connect these top-level ports to FPGA pins in XPS, just like with any pcore which needs off-chip connections. Look at the OFDM reference design's system assembly view (or MHS file) to see this interconnect.
zrcao wrote:
(B) What is the VGC settling time for both coarse gain and fine_grained gain?
(C) The settling time for increasing gain and decreaing gain are same or different?
Our AGC core settles within 36-48 samples from the initial packet detection event. The settling time of the MAX2829's amplifiers are specified by Maxim. I can't post the actual numbers; you'll have to refer to the MAX2829 datasheet for the details.
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murphpo wrote:
The packet detector and AGC cores are split for NDA reasons.
Theoretically, you can design your own AGC and packet detector algorithms, right? The NDA covers their algorithm and implementation.
In order to design customized AGC, the necessary information includes all the pin connection (gateway blocks), data type for each gateway, and the function of each gateway. Those shouldn't be covered by NDA. I think it is possible for users to dig into the reference model, with the help of Maxim 2829 datasheet, to find out all the interface information. But thsi will be time consuming and may not be accurate.
It seems to me that WARP team might already have a list of interface definition necessary for AGC/RSSI control. If this can be posted on WARP repository without releasing the detail of AGC algorithm, it will be very helpful for WARP users without NDA.
Last edited by zrcao (2007-Mar-15 22:32:21)
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zrcao wrote:
Theoretically, you can design your own AGC and packet detector algorithms, right? The NDA covers their algorithm and implementation.
Definitely. In fact, this will be required for any PHY that doesn't look like 802.11a.
zrcao wrote:
It seems to me that WARP team might already have a list of interface definition necessary for AGC/RSSI control. If this can be posted on WARP repository without releasing the detail of AGC algorithm, it will be very helpful for WARP users without NDA.
It's on our list of things to add to the documentation. In the mean time, it should be straightforward to infer the interfaces from the OFDM reference design. The signals routed to the AGC and packet detection cores have meaningful names and all connect to the radio boards through the radio_bridge cores. Custom AGC/packet detection cores would need to source/sink the exact same signals.
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