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#1 2016-Nov-04 04:12:05

gmkim
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Registered: 2016-Jul-19
Posts: 27

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Last edited by gmkim (2020-Aug-17 20:06:07)

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#2 2016-Nov-04 13:32:47

murphpo
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From: Mango Communications
Registered: 2006-Jul-03
Posts: 5159

Re: .

The WARPLab Reference Design is an FPGA design that combines custom hardware cores and a MicroBlaze CPU. The custom cores are built with either raw HDL or System Generator. The MicroBlaze CPU runs software compiled in the SDK. If you need to modify one of the custom cores, then you must modify the core source, update the core in XPS, rebuild the design in XPS, then re-export the updated hardware design to the SDK. If you only need to modify the C code that runs in the MicroBlaze you can use just the SDK - no need to use XPS if you're not modifying the hardware design.

The radio_controller driver controls the RF interface Tx/Rx state in C code. You can probably achieve your custom behavior with only C code changes. The SDK_Workspace folder in the reference design archive is the best place to start for creating an SDK project. Our getting started examples describe the SDK flow in general.

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#3 2016-Nov-06 08:25:11

gmkim
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Registered: 2016-Jul-19
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Re: .

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Last edited by gmkim (2019-Jul-17 05:58:46)

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#4 2016-Nov-07 09:15:50

chunter
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From: Mango Communications
Registered: 2006-Aug-24
Posts: 1212

Re: .

gmkim wrote:

You said "You can probably achieve your custom behavior with only C code changes.", then do I just need the SDk program?
If the answer is yes, I think I don't need full license of ISE, do I?

That's right, you can download the SDK without a full license of ISE. Make sure you download the 14.4 version and not anything newer if you want to use our reference designs.

gmkim wrote:

1. In "Introduction to SDK" tutorial, they just explain how to program FPGA with JTAG cable.
    If I want to use SD card to configurate FPGA, how can I make bin file with SDK program?

Our SD card how-to documentation explains how to do this. You can convert a .bit file from the SDK to a .bin file with a command line tool.

gmkim wrote:

2. What is custom hardware cores? Another chip?
    I canít understand clearly what difference between custom core and custom behavior with C code.

Custom hardware cores are designs that run in FPGA fabric. This is best suited for real-time applications like physical layer processing. Behavior specified in C code can run in a microprocessor core. This is best suited to for controlling the custom hardware cores and implementing complex state behaviors like medium access control. The two (C-code and custom cores) are not alternatives of one another -- they can both be used in a single design. For example, the 802.11 Reference Design hare custom hardware cores that implement the OFDM Tx and Rx PHY as well as two MicroBlaze processors that run the C-code for the 802.11 MAC.

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#5 2016-Nov-07 11:33:30

gmkim
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Registered: 2016-Jul-19
Posts: 27

Re: .

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Last edited by gmkim (2019-Jul-17 05:59:39)

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#6 2016-Nov-08 09:48:19

murphpo
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From: Mango Communications
Registered: 2006-Jul-03
Posts: 5159

Re: .

I want WARP board to listen channel continuously and calculate signal whether any packet is received without host PC.

This describes a real-time Rx physical layer (PHY) design. Our 802.11 Reference Design is one example of such a design. The WARPLab Reference Design does not implement a real-time Rx PHY. Instead WARPLab buffers Rx samples in real-time, then offloads them to MATLAB for offline (non-real-time) processing.

Is it possible to make this design of FPGA only with SDK program?
I think this is real-time application but need microprocessor to calculate.
Do I need both C-code and custom cores? (Sorry, I am very confused)

It depends on how sophisticated the Rx processing is. In general we do not recommend using the MicroBlaze CPU to process I/Q samples. All of our designs use the MicroBlaze to manage custom cores in the FPGA fabric; these cores operate on the I/Q samples in real time.

Is the Xilinx only tool for implementing the design in the FPGA of WARP?

Yes, you must use the Xilinx tools to create or customize designs for the Xilinx FPGA on WARP hardware.

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#7 2016-Nov-09 07:36:33

gmkim
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Registered: 2016-Jul-19
Posts: 27

Re: .

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Last edited by gmkim (2019-Jul-17 06:00:46)

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#8 2016-Nov-09 09:03:44

murphpo
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From: Mango Communications
Registered: 2006-Jul-03
Posts: 5159

Re: .

If I want to use the MicroBlaze CPU to process I/Q samples though you don't recommned it, where should I start? (I will use WARPLab FPGA design with SDK)
What part of C code do I need to modify? (There are so many codes...)

First, the MicroBlaze CPU is not fast enough to process a 40MSps IQ stream in real time. If processing samples in the MB CPU is a requirement of your application, you will need to design some way to reduce the processing burden (i.e. decimate the 40MSps stream to a lower sampling rate, process less than 100% duty cycle, etc).

Second, this would require substantial modifications to the WARPLab Reference Design. The WARPLab design is optimized for moving IQ samples between the RF interfaces, on-chip buffers, off-chip DRAM and the Ethernet MAC. All sample transfers are executed by DMA cores - the MicroBlaze C code controls the DMAs but does not directly access any samples in memory. It is definitely possible to build this, but I cannot tell you exactly how as we have never built such a design.

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#9 2016-Nov-10 05:07:19

gmkim
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Registered: 2016-Jul-19
Posts: 27

Re: .

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Last edited by gmkim (2019-Jul-17 06:01:27)

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#10 2016-Nov-10 07:22:09

murphpo
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From: Mango Communications
Registered: 2006-Jul-03
Posts: 5159

Re: .

Universities can request a tools license donation via the Xilinx University Program. Many universities already have site licenses via the XUP. I would definitely recommend checking these options before buying a new license.

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