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Hi,
This is Kiruba Subramani from UT Dallas. I designed a custom RF daughterboard for WARP V2 FPGA board and recently I started working with WARP V3. In an attempt to reuse the daughterboard, I have designed an Interposer board that performs logic level shifting (3.3v on WARP v2 to 2.5v on WARP v3) and power regulation (5v for WARP v2 daughtercards, 12v/3.3v supplied by the FMC slot). So far I have managed to complete the following tasks by following your website and forum (https://warpproject.org/forums/viewtopic.php?id=2831)
1. Create custom Pcore to connect RF board signals (Enable, resets, SPI, data converter) to FPGA pins
2. Configure individual ICs through SPI interface from the custom core
3. Verified ADC output and DAC input signal integrity through loopback tests.
I am left with interfacing ADC output and DAC input with the 802.11 reference design, which will allow me to use the custom board as additional RF front ends (TX and RX). Following are my questions regarding this interface
1. My RF board uses a 200MHz sampling clock generated by an on board crystal oscillator. I am using AD9513 to fanout the clock to ADC(ADS5527) and DAC (AD9747). My data converter ICs send a clockout signal
to the FPGA for synchronization. How can I interface this high rate signal with WARP baseband logic (WARP uses a 20MSps data rate)?
2. I have the option to reduce the sampling clock to 40MHz. Can I use this frequency and use a decimation filter (2x downsample) to avoid aliasing and ensure proper signal interface between baseband logic and RF board?
3. If using decimation filter, should I implement it in simulink and synthesize it or should I be implementing it directly in XPS pcore?
Appreciate your help!
Regards,
Kiruba
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One important aspect of the 802.11 ref FPGA design is that the FPGA is clocked by the same clock source as the ADC/DACs. The entire ref design (MicroBlazes, interconnects, memory, PHY pipelines, etc) is synchronous to the sampling clock, all driven by the 80MHz TCXO on the WARP v3 board. The 80MHz TCXO drives the AD9512 buffers, which drive the radio reference inputs, AD9963 reference inputs and the FPGA. If possible, you should aim for the same basic scheme. Keeping the FPGA design synchronous to the sampling clock will greatly simplify the overall design.
For reference the 802.11 ref design on WARP v3 uses this I/Q pipeline:
Tx: wlan_phy_tx -> w3_ad_bridge -> AD9963(interp filters -> DACs)
Rx: AD9963(ADCs -> decimation filters) -> w3_ad_bridge -> wlan_agc -> wlan_phy_rx
As of the v1.5 design the AGC and PHY cores support sampling rates up to 1/4 of the core clock rates. We clock the PHY cores at 160MHz in the ref FPGA design, supporting up to 40MSps at the PHY/AGC I/Q interfaces. The cores support changing the sampling rate at run time. The w3_ad_bridge core generates a "samp_ce" signal used by the Tx and AGC cores to qualify the I/Q samples. The w3_ad_bridge generates samp_ce from the AD9963 TRXCLK signal. The TRXCLK rate is set by configuring the AD9963 data path. For 20MHz mode we clock the ADC/DACs at 40MHz and enable 2x interp/decimation filters in the AD9963, giving TRXCLK=20MHz. For 40MHz mode we disable the interp/decimation filters, giving TRXCLK=40MHz.
Implementing interp/decimation filters in the FPGA would be straightforward. Xilinx provides the FIR Compiler core which supports multi-rate filter implementations. The System Generator wrapper for the FIR Compiler is great. For 2x rate change you can use a halfband FIR filter (very efficient architecture). In fact, you could use the same halfband filters as the AD9963; see the AD9963 for the coefficients. You could implement the filters in the wlan_agc (decimation) and wlan_phy_tx (interpolation) cores at the interfaces which currently connect to the w3_ad_bridge core. Alternatively you could build a new pcore with just the rate-change filters and insert this between the ADC/DACs and AGC/Tx cores.
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