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#1 2017-Mar-25 02:16:04

harryzwh
Member
Registered: 2016-Jul-04
Posts: 8

Reduce the quantization levels

Hi

We am now working on WARPLab 7.7.0 and we want to evaluate the effect of number of quantization level as well as reduce the transmit latency. We want to reduce the number of bits that used to represent each IQ sample (i.e. dropping some bits in the lower position).

We plan to do the modification in C code since we are not familiar with FPGA. By reading the C code, we know that the moving of data between memory and Ethernet cache is done by DMA which means there is no way to modified the data in DMA. So, I think we need to add a function to modified the data before it actually sent to Ethernet. Then my question is

1) Is is possible to use CPU to preform the above process? In order the reduce the amount of traffic, we already modified the FPGA so that the bandwidth is reduced to 10MHz and the sample rate in CPU is also 10M sample/s since we do interpolation and decimation in FPGA.

2) If CPU is not capable to handle the above process, is it possible to implement it in FPGA? Which parts we need to modify?

Since we have build our own MEX function to handle simple transmission, the program in computer side will not be a big problem.

Thank you

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#2 2017-Mar-25 11:16:42

murphpo
Administrator
From: Mango Communications
Registered: 2006-Jul-03
Posts: 5159

Re: Reduce the quantization levels

An key part of the WARPLab Reference Design architecture is that the MicroBlaze CPU never touches individual I/Q samples. The MicroBlaze manages the DMA transfers between Ethernet and DRAM (via the Ethernet's axi_dma) and between DRAM and the warplab_buffers core (via the axi_cdma core). These DMA transfers are triggered/monitored by the MicroBlaze C code, but the I/Q data itself never passes through the MicroBlaze core. This design enables the required throughput for simultaneous 40MSps Tx/Rx across multiple RF interfaces. Given this, I definitely recommend that you avoid any I/Q sample processing in the MicroBlze C code.

We am now working on WARPLab 7.7.0 and we want to evaluate the effect of number of quantization level as well as reduce the transmit latency. We want to reduce the number of bits that used to represent each IQ sample (i.e. dropping some bits in the lower position).

The WARPLab Ref Design represents each I/Q sample as a 32-bit value (16-bits each for I and Q). The assumption of 32-bits-per-sample is deeply embedded in the M code, mex C code, MicroBlaze C code and warplab_buffers FPGA logic. Changing to a different representation is certainly possible, but you will need to study and modify parts of the entire design (M, mex C, MicroBlaze C and Sysgen model) to adopt the new representation.

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