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Dear Sir,
I have a question about using CM-PLL/CM-MMCX for multiple receiver time sync. The hardware is 4 WARP V3 (three serves as the receiver array). The library is WARPLab V7.7.1.
1): I want to make sure that the CM-MMCX indeed CANNOT be used for multiple WARP (>3) time sync, right?
2): I know the CM-PLL works for multiple WARPs. However, I notice that in the 8x2 array example, the hardware equipment list does not include the twisted pair cable assembly. So does that mean I just need to connect the CM-PLL on each board using SFSD-series cable and configure the SIP switch without using the twisted cable. If yes, in the code, shall I still need to configure the triggerIn/tirggerOut of the debug header for time sync? I'm confused here because I saw in the 8x2 antenna array example you used the twisted cable and configure port in the code. I know it works for the CM-MMCX, but in the code (line 52) there is a comment "work with either the CM-PLL (where output P0 directly connects to input P0) ....". So it seems the configuration of the debug header is required as well for CM-PLL.
Thanks for your help!
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After checking the previous similar problems: I make the following start-topology configuration, could you help to point out whether it is correct:
Target: Building 2 Tx (1 WARP board), 16 Rx (4 WARP board node_Rx1, node_Rx2, node_Rx3, node_Rx4) system with WARP V3, WARPLab7.7.1. Synchronizing the 4 Rx board.
Cable connection: Each Rx board is equipped with a CM-PLL. I use three twisted cables, with each connecting node_Rx1 P8 and node_Rx2 P15, node_Rx1 P9 and node_Rx3 P15, node_Rx1 P10 and node_Rx4 P15, respectively.
On the code part, I write as follows:
wl_triggerManagerCmd(node_tx, 'output_config_input_selection', [trig_out_ids.BASEBAND, trig_out_ids.AGC], [trig_in_ids.ETH_A]);
wl_triggerManagerCmd(node_rx1, 'output_config_input_selection', [trig_out_ids.BASEBAND, trig_out_ids.AGC, trig_out_ids.EXT_OUT_P0,trig_out_ids.EXT_OUT_P1,trig_out_ids.EXT_OUT_P2], [trig_in_ids.ETH_A]);
wl_triggerManagerCmd([node_rx2,node_rx3,node_rx4], 'output_config_input_selection', [trig_out_ids.BASEBAND, trig_out_ids.AGC], [trig_in_ids.EXT_IN_P3]);
If it is correct, could you help to explain how to set the delay, debounce of Tx and Rxs hereafter?
Another question is about using the CM-PLL cable (SFSD-05-28-F-8-DR-NUS) to do a daisy chain. I configuration the hardware part like this:
Cable connection: connecting Out of CM-PLL on node_Rx1 to In of CM-PLL on node_Rx2, connecting Out of CM-PLL on node_Rx2 to In of CM-PLL on node_Rx3, connecting Out of CM-PLL on node_Rx3 to In of CM-PLL on node_Rx4.
SIP switch of CM-PLL of node_Rx1: set to up up down up down up (On board, enabled, first)
SIP switch of CM-PLL of node_Rx2: set to up down up up up down (off board, enabled, middle)
SIP switch of CM-PLL of node_Rx3: set to up down up up up down (off board, enabled, middle)
SIP switch of CM-PLL of node_Rx4: set to down down up up up down (off board, disabled, last)
Is it correct? Then how to set up the configuration on the code part?
Thanks for your help!
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Cable connection: Each Rx board is equipped with a CM-PLL. I use three twisted cables, with each connecting node_Rx1 P8 and node_Rx2 P15, node_Rx1 P9 and node_Rx3 P15, node_Rx1 P10 and node_Rx4 P15, respectively.
This is not the correct setup when using the CM-PLL. To synchronize nodes with CM-PLL modules you must use ribbon cables connected to the IN and OUT headers on the CM-PLL. These cables route both the reference clock signal (synchronizes the sampling and RF clocks) and digital I/O (synchronizes the WARPLab state machines via trigger in/out). You should not use the WARP v3 debug header for trigger I/O when you're using CM-PLL modules.
Refer to the WARPLab user guide Hardware Configuration page for the SIP switch settings for the First, Middle, and Last positions of nodes in a daisy chain of CM-PLL modules.
Then how to set up the configuration on the code part?
You must write your WARPLab script to configure the trigger inputs/outputs depending on which nodes you want to act as trigger sources and sinks.
For a 4-node array setup with a daisy chain via CM-PLL modules, you probably want the head node to use Ethernet as its trigger source. The head node should connect the Ethernet trigger to that node's Baseband and AGC cores. It should also connect the Ethernet trigger to the CM-PLL trigger output.
The Middle nodes in the daisy chain should connect the CM-PLL trigger input to the Baseband and AGC cores. These nodes should also connect the CM-PLL trigger input to the CM-PLL trigger output, so the trigger signal propagates down the chain.
The Last node in the daisy chain should also connect the CM-PLL trigger input to the Baseband and AGC cores. However this nodes should not connect any trigger sources to the CM-PLL outputs as there are no connections to this node's CM-PLL OUT header.
Once you've made all these connections you can adjust the trigger output delays at the Head and Middle nodes to align the shared trigger event across the Head/Middle/Last nodes. The delay values will depend on your cable lengths.
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Thanks for your reply! Really appreciate.
When you say "The head node should connect the Ethernet trigger to that node's Baseband and AGC cores. It should also connect the Ethernet trigger to the CM-PLL trigger output." Did you mean configuring using the code like wl_triggerManagerCmd([node_rx1], 'output_config_input_selection', [trig_out_ids.BASEBAND, trig_out_ids.AGC], [trig_in_ids.ETH_A])? By the way, what is the API name of CM-PLL trigger input and CM-PLL trigger output in the WARP_Lab?
Thanks!
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A few example configurations for mapping trigger inputs to outputs:
% Connect ETH_A trigger input to BASEBAND and AGC trigger outputs wl_triggerManagerCmd([node_rx1], 'output_config_input_selection', [trig_out_ids.BASEBAND, trig_out_ids.AGC], [trig_in_ids.ETH_A]) % Connect ETH_A trigger input to BASEBAND, AGC, P0 trigger outputs wl_triggerManagerCmd([node_rx1], 'output_config_input_selection', [trig_out_ids.BASEBAND, trig_out_ids.AGC, trig_out_ids.EXT_OUT_P0], [trig_in_ids.ETH_A]) % Connect P0 trigger input to BASEBAND, AGC, P0 trigger outputs wl_triggerManagerCmd([node_rx1], 'output_config_input_selection', [trig_out_ids.BASEBAND, trig_out_ids.AGC, trig_out_ids.EXT_OUT_P0], [trig_in_ids.EXT_IN_P0])
By the way, what is the API name of CM-PLL trigger input and CM-PLL trigger output in the WARP_Lab?
The CM-PLL trigger I/O signals are use the same trigger IDs as the debug header, named EXT_OUT_Pn (outputs) and EXT_IN_Pn (inputs), for n = [0..3].
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