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Hello,
I'm was wondering if someone could help me with figuring out the best way to implement chipscope with the 802.11 reference design so that I can analyze the IQ signals on RFA or RFB, preferably both.
When I tried implementing the chipscope into my design through XPS the bitstream generation threw errors about the JTAG_CHAIN attribute setting. I then started over and tried again through Planahead but I ran into trouble there due to my inexperience with the tool. If anybody has any advice or could point me towards some helpful documentation it would be much appreciated.
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The 802.11 Ref Design for WARP v3 includes a ChipScope ILA core in the Rx PHY. This ILA has access to the I/Q signals for the RF A ADCs at the Rx PHY input. If you run ChipScope Analyzer and connect to the 802.11 ref design in hardware it should find one ILA with many bits of inputs. You can import the ref design .cdc file (in the /pcores/wlan_phy_rx.../mdlsrc/ folder) to apply the System Generator signal names/formats to the ILA inputs. In the Rx PHY model the ChipScope core is in its own subsystem at the top level. All the various internal PHY signals are routed to the ChipScope core with Simulink From/Goto blocks.
The error you're seeing when adding a new ChipScope core is caused by a conflict with the ChipScope cores inserted by System Generator. Sysgen inserts an ILA and ICON core. The ICON core takes ownership of the BSCAN (internal JTAG) interface. You can only instantiate one ICON per bitstream. When you instantiate an ICON manually you can connect it to many ILAs. When Sysgen instantiates the ICON it is only connected to the ILAs in the Sysgen design. This is an unfortunate limitation.
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