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#1 2017-Jul-31 22:15:53

Registered: 2014-Oct-02
Posts: 20

9963 ADC Clock Frequency


I was wondering what the frequency of the clock which is connected to the AD9963 is, i.e. RF1_AD_CLK_P ? Thanks.



#2 2017-Jul-31 23:12:14

From: Mango Communications
Registered: 2006-Jul-03
Posts: 5159

Re: 9963 ADC Clock Frequency

The clock is derived from the 80MHz TCXO. The frequency at the AD9963 input depends on the FPGA design.

The AD9963 clock is driven by the sampling clock buffer (AD9512; refer to the WARP v3 clocking user guide for details). The AD9512 clock source is the 80MHz TCXO. Each AD9512 output has a programmable divider. In our reference designs these dividers are configured from the C code running in the MicroBlaze. In the 802.11 Ref Design, for example, the divider setting depends on the PHY sampling rate, as configured in wlan_platform_low_set_samp_rate(). For 20MSps mode, for example, the AD9963 clock input is driven at 40MHz, and the AD9963 interpolation/decimation filters are enabled.



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