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Hi.
We are updating design tools(ISE/EDK) from 8.2 to 10.x.
I am wondering if our HW setup is up to it as our FPGA boards are ver. 1.2, radio boards are ver. 1.4 and clock boards are ver 1.0.
Q: Would the newest ref design work in this HW setup? If not can we do something get it work?
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I believe your clock boards do not have 40MHz oscillators. The newest reference design uses the now-standard 40MHz oscillator as the primary clock, deriving every other clock from it. It would be possible to re-work the reference design to use the FPGA board's 100MHz oscillator (like reference design v04).
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Thanks.
I have problem concerning if our old ref.design04 code is going to work with the newer setup?
With newer setup i mean clock board with 40 MHz oscillators.
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The stock ref design v04 hardware platform uses:
a) The FPGA board's 100MHz oscillator as the master logic and sampling clock
b) A 50MHz sampling clock (derived from the 100MHz oscillator) delivered to the radio boards via the daughtercard headers; this requires radios configured to receive their clock via the daughtercard connectors.
Newer ref designs use:
a) The clock board's 40MHz oscillator as the master clock
b) A 40MHz sampling clock delivered to the radio boards via twisted pair cables connected directly to the clock board; this requires radios configured to receive their clock via the 4-pin header, *not* the daughtercard connectors. This is the configuration of new radio boards.
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Thanks for the info.
So basically if i would download ref.design04 bitstream to newer boards (**) could it work ? With or without the twisted cable.. or is the design so different on the clock board that it's not possible.
As i don't have any way to test this in real life as our clock boards are ver. 1.0. So input would be much appreciated.
**FPGA board ver. 1.2, radio board ver. 1.4 and clock board ver 1.1.
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Ref design v04 won't work as-is on new kits, because new kits use radio boards configured to receive their sampling clock from the clock board.
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