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Hi,
I noticed the phase variation over time for antennas on different boards is larger than that for antennas on the same board. I.e. if I transmit a narrowband signal from RFA and receive on RFD, both on board 1, the phase maximum variation over 250 transmissions is 1.6 degrees. However, if I receive on RFD board 2, the maximum variation is 3.4 degrees. The two boards are time (via a GPIO trigger) and frequency synced (board 2 uses board 1's clock).
My first guess was due to ambiguities in the trigger, but I find the variation does not increase for higher baseband frequencies which I would expect if the trigger was an issue, correct? Any clue what else could be the cause? Clock sharing? Phase noise?
Best,
Abeer
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My first guess is the WARPLab trigger as well. Are the phase measurements bimodal (i.e. grouping around two values in the range of [0, 3.4] degrees)? If so that could support the theory that the trigger is introducing an ambiguity. Even though your nodes are sharing sampling and carrier clocks, their relative phase is arbitrary and fixed. So, it could be that your GPIO trigger is arriving at just the wrong time between samples. Sometimes it gets latched on the earlier sample; sometimes on the later. The output_config_delay command can be used to delay the output trigger to shift it into a capture window that is deterministic.
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Hm the output_config_delay command didn't help.
Actually turns out it isn't a trigger issue, because over a long enough single run I see the same variations; they only exist for RF chains on the synchronized board that is not transmitting. The variations are very regular, and appear as phase difference spikes at approximately 60 Hz.
The only other shared signal is the clock. Does the RF reference buffer (AD9512) resync to the offboard incoming clock signal periodically in some sense?
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Observing an issue at the power line rate (60Hz) is suspicious. It sounds odd but try your experiment again with the lights off - fluorescent lights can be a source of EMI. You could also use a good oscilloscope to observe the clock signal at the input to the node, looking for some transient that corresponds to the phase change.
Does the RF reference buffer (AD9512) resync to the offboard incoming clock signal periodically in some sense?
No. The AD9512 ICs on the WARP v3 board are configured as buffers - every clock transition at their inputs is passed through to the outputs. If the outputs are double-clocking or skipping cycles, it's almost certainly because of the clock input.
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