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#1 2018-Feb-03 11:46:40

lizhuqi
Member
Registered: 2017-Oct-17
Posts: 14

Phase offset aliasing after CM-PLL synchronization among multiple Rx;

Hi Sir,

I am designing a system that uses one warp to transmit and four warps to receive, which requires four RXs to be time-synchronized.

To verify CM-PLL synchronization among multiple RXs really works, I use the configuration in the following figure.

https://drive.google.com/open?id=1laGi- … 0qwf_h28ye

In the figure, the four receiving warps are synchronized with CM-PLL unit. All the ports are configured to be on the same channel. The transmitter and receiver are connected with wired cables and splitter.

To make the verification, I sent 200 packets and plot the histogram for their CSI phase difference between the corresponding port in different warps. The result is shown in the following figure

https://drive.google.com/open?id=1momgj … FYSH3FsJzH

Judging from the plot, we can see two groups of phase offset, the difference of which is pi.


However, when we plot the histogram for the CSI phase difference between the different ports in same warp, we can find the aliasing effect almost disappear. The figure is shown in the following link

https://drive.google.com/open?id=1sByQv … nZqGi97DBt


So I am wondering whether CM-PLL synchronization causes this aliasing effect?? and is there any way to eliminate this effect??

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#2 2018-Feb-05 09:52:29

chunter
Administrator
From: Mango Communications
Registered: 2006-Aug-24
Posts: 1184

Re: Phase offset aliasing after CM-PLL synchronization among multiple Rx;

What project are you using for these tests. Is it WARPLab? If so, how are you triggering all of the receivers such that they start at the same time? You'll want to use twisted pair cables between the debug headers of your receivers like this example. If you are doing this and are still seeing the bimodal phase differences, a couple of explanations come to mind:

1) Are you calling "wl_initNodes()" or are you tuning to a channel in between each packet? Either of those commands will reset the PLL and cause an arbitrary phase shift among your nodes.

2) You might be seeing a setup or hold violation on the trigger input in one or more of your receivers. If the trigger signal arrives at just the wrong time between samples, there could be an +/- 1 sample ambiguity on when a receiver starts relative to the others. That delay could manifest as a phase shift in your experiments. You can mitigate the issue by trying different delays with the output_config_delay command to try to shift the trigger signal out of the setup or hold violation window between samples.

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