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#1 2018-Jun-25 08:10:16

vutran
Member
Registered: 2017-Jul-01
Posts: 35

CM-PLL Trigger Delay

Hi,

I'm using 2 WARP and use CM-PLL to synchronize the two and I have 2 question related to the synchronization.
(1) As in the Sysgen model of the trigger module, there should be some delay between the two WARPs, so they are not start indeed at the same time, is it correct? For example, the trig_0_out (which trigger the WARPLab buffer) is active at the same time the cm_pll_0_out active (or 1 sample different), and it takes several cycle to activate the trig_0_out in the second WARP.
(2) Is there any way I can determine the delay (in cycles) of the CM-PLL trigger so that I can insert a delayed path to make the 2 WARPs triggered indeed at the same time (+/- 1 cycle is ok)?

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#2 2018-Jun-25 08:56:05

murphpo
Administrator
From: Mango Communications
Registered: 2006-Jul-03
Posts: 4924

Re: CM-PLL Trigger Delay

I believe that in the WARPLab Reference Design there is a ~9 cycle latency from trigger source to trigger sink when using the clock module trigger signals between boards (mentioned in the user guide). This latency is primarily IOB and pipeline registers on both nodes. The cable adds a little latency too, possibly another cycle if it's long enough.

The best way to observe latencies in hardware is with an oscilloscope. For example you can configure both nodes to route a copy of its trigger to another debug pin, then observe these pins simultaneously on the scope. The trigger sink would apply minimum delay from trigger in -> debug output. The trigger source could then be adjusted to implement the same delay.

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