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I was just wondering if, within Xilinx Platform Studio, it was doable to add BRAM to either the 802.11 or Warplab reference designs, since oftentimes by attempting to add too much additional code to the microblaze, I would get errors like: region `microblaze_0_i_bram_ctrl_microblaze_0_d_bram_ctrl' overflowed by 48236 bytes.
So, for the 802.11 reference design, I attempted to add more 2 blocks in the following manner in my system.mhs file:
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = mb_high_dlmb_bram_cntlr_2
PARAMETER HW_VER = 3.10.c
PARAMETER C_BASEADDR = 0x00040000
PARAMETER C_HIGHADDR = 0x0005FFFF
BUS_INTERFACE SLMB = mb_high_dlmb
BUS_INTERFACE BRAM_PORT = mb_high_dlmb_bram_cntlr_2_BRAM_PORT
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = mb_high_ilmb_bram_cntlr_2
PARAMETER HW_VER = 3.10.c
PARAMETER C_BASEADDR = 0x00040000
PARAMETER C_HIGHADDR = 0x0005FFFF
BUS_INTERFACE SLMB = mb_high_ilmb
BUS_INTERFACE BRAM_PORT = mb_high_ilmb_bram_cntlr_2_BRAM_PORT
END
BEGIN bram_block
PARAMETER INSTANCE = mb_high_lmb_bram_2
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = mb_high_dlmb_bram_cntlr_2_BRAM_PORT
BUS_INTERFACE PORTB = mb_high_ilmb_bram_cntlr_2_BRAM_PORT
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = mb_high_dlmb_bram_cntlr_3
PARAMETER HW_VER = 3.10.c
PARAMETER C_BASEADDR = 0x00060000
PARAMETER C_HIGHADDR = 0x0007FFFF
BUS_INTERFACE SLMB = mb_high_dlmb
BUS_INTERFACE BRAM_PORT = mb_high_dlmb_bram_cntlr_2_BRAM_PORT
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = mb_high_ilmb_bram_cntlr_3
PARAMETER HW_VER = 3.10.c
PARAMETER C_BASEADDR = 0x00060000
PARAMETER C_HIGHADDR = 0x0007FFFF
BUS_INTERFACE SLMB = mb_high_ilmb
BUS_INTERFACE BRAM_PORT = mb_high_ilmb_bram_cntlr_3_BRAM_PORT
END
BEGIN bram_block
PARAMETER INSTANCE = mb_high_lmb_bram_3
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = mb_high_dlmb_bram_cntlr_3_BRAM_PORT
BUS_INTERFACE PORTB = mb_high_ilmb_bram_cntlr_3_BRAM_PORT
END
Is this the general way to do it? I recieved some errors when I attempted to generate the bitstream, which I think may have to do with these blocks not being specified in the # Basic floorplanning section of the system.ucf file.
Is it at all possible to add additional bram then to either of these designs?
Thanks in advance for any help!
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That is the correct way to add BRAM to the ILMB/DLMB busses. But I would guess it will be difficult for the design to meet timing with that much BRAM attached to the LMB. The path between the local memory and MicroBlaze pipeline is often the critical timing path during implementation. With more BRAM the worst-case path is probably longer.
Timing constraints are the reason the 802.11 Design for WARP v3 uses two 128kB BRAM blocks instead of one 256kB block. One block would be easier (less BMM file hacking required), but in our experience the tools could not reliably meet 160MHz timing with a single 256kB block attached to the CPU High LMB. The current architecture of two 128kB blocks has been robust. But I would not be surprised if >2 128kB blocks is a timing challenge.
Have you looked at other ways to reduce code size? A few ideas:
-Set the compiler optimization to "-Os"
-Disable MAC framework features you don't need, like wlan_exp or Ethernet bridging. See wlan_mac_high_sw_config.h for details.
-Always use "xil_printf()", not "print()" or "printf()"
-Examine the linker map file (<sdk_proj>/Debug/executable.map) to identify code/data sections that are unexpectedly big. We use this to track down overlooked debug code.
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