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Hi,
I am developing based on the latest version of warplab with warp v3. I only modified warp_buffers. I got timing constraint error when compiling with XPS. I used Timing Analyzer, which showed the timing error comes from somewhere else, as attached below.
The only suspicious thing I did is I added quite a lot (~130) new register readings from memory (inside Memory-based Registers).
Do you have any idea on what should I modify to make it work?
Thanks,
Lu
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Timing constraint: TS_clock_generator_ProcBusSamp_Clocks_clock_generator_ProcBusSamp_Clocks_SIG_MMCM0_CLKOUT1 = PERIOD TIMEGRP "clock_generator_ProcBusSamp_Clocks_clock_generator_ProcBusSamp_Clocks_SIG_MMCM0_CLKOUT1" TS_samp_clk * 2 HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
3780853 paths analyzed, 317776 endpoints analyzed, 3 failing endpoints
3 timing errors detected. (3 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is 6.531ns.
--------------------------------------------------------------------------------
Slack (setup path): -0.281ns (requirement - (data path - clock path skew + uncertainty))
Source: axi_interconnect_buffers/axi_interconnect_buffers/crossbar_samd/gen_samd.crossbar_samd/gen_crossbar.addr_arbiter_aw/m_mesg_i_20 (FF)
Destination: axi_interconnect_buffers/axi_interconnect_buffers/mi_register_slice_bank/gen_reg_slot[9].register_slice_inst/aw_pipe/storage_data2_44 (FF)
Requirement: 6.250ns
Data Path Delay: 6.406ns (Levels of Logic = 0)
Clock Path Skew: -0.067ns (1.491 - 1.558)
Source Clock: axi_bram_ctrl_0_BRAM_PORTA_0_BRAM_Clk rising at 0.000ns
Destination Clock: axi_bram_ctrl_0_BRAM_PORTA_0_BRAM_Clk rising at 6.250ns
Clock Uncertainty: 0.058ns
Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.092ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: axi_interconnect_buffers/axi_interconnect_buffers/crossbar_samd/gen_samd.crossbar_samd/gen_crossbar.addr_arbiter_aw/m_mesg_i_20 to axi_interconnect_buffers/axi_interconnect_buffers/mi_register_slice_bank/gen_reg_slot[9].register_slice_inst/aw_pipe/storage_data2_44
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X56Y73.CQ Tcko 0.322 axi_interconnect_buffers/DEBUG_CB_MF_AWADDR<15>
axi_interconnect_buffers/axi_interconnect_buffers/crossbar_samd/gen_samd.crossbar_samd/gen_crossbar.addr_arbiter_aw/m_mesg_i_20
SLICE_X64Y173.AX net (fanout=24) 6.084 axi_interconnect_buffers/DEBUG_CB_MF_AWADDR<14>
SLICE_X64Y173.CLK Tdick 0.000 axi_interconnect_buffers/axi_interconnect_buffers/mi_register_slice_bank/gen_reg_slot[9].register_slice_inst/aw_pipe/storage_data2<47>
axi_interconnect_buffers/axi_interconnect_buffers/mi_register_slice_bank/gen_reg_slot[9].register_slice_inst/aw_pipe/storage_data2_44
------------------------------------------------- ---------------------------
Total 6.406ns (0.322ns logic, 6.084ns route)
(5.0% logic, 95.0% route)
--------------------------------------------------------------------------------
Slack (setup path): -0.066ns (requirement - (data path - clock path skew + uncertainty))
Source: axi_interconnect_buffers/axi_interconnect_buffers/crossbar_samd/gen_samd.crossbar_samd/gen_crossbar.addr_arbiter_aw/m_mesg_i_32 (FF)
Destination: axi_interconnect_buffers/axi_interconnect_buffers/mi_register_slice_bank/gen_reg_slot[9].register_slice_inst/aw_pipe/storage_data1_56 (FF)
Requirement: 6.250ns
Data Path Delay: 6.182ns (Levels of Logic = 1)
Clock Path Skew: -0.076ns (1.470 - 1.546)
Source Clock: axi_bram_ctrl_0_BRAM_PORTA_0_BRAM_Clk rising at 0.000ns
Destination Clock: axi_bram_ctrl_0_BRAM_PORTA_0_BRAM_Clk rising at 6.250ns
Clock Uncertainty: 0.058ns
Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.092ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: axi_interconnect_buffers/axi_interconnect_buffers/crossbar_samd/gen_samd.crossbar_samd/gen_crossbar.addr_arbiter_aw/m_mesg_i_32 to axi_interconnect_buffers/axi_interconnect_buffers/mi_register_slice_bank/gen_reg_slot[9].register_slice_inst/aw_pipe/storage_data1_56
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X55Y75.CQ Tcko 0.283 axi_interconnect_buffers/DEBUG_CB_MF_AWADDR<27>
axi_interconnect_buffers/axi_interconnect_buffers/crossbar_samd/gen_samd.crossbar_samd/gen_crossbar.addr_arbiter_aw/m_mesg_i_32
SLICE_X57Y164.B1 net (fanout=24) 5.842 axi_interconnect_buffers/DEBUG_CB_MF_AWADDR<26>
SLICE_X57Y164.CLK Tas 0.057 axi_interconnect_buffers_M_AWADDR<318>
axi_interconnect_buffers/axi_interconnect_buffers/mi_register_slice_bank/gen_reg_slot[9].register_slice_inst/aw_pipe/Mmux_S_PAYLOAD_DATA[67]_storage_data2[67]_mux_3_OUT521
axi_interconnect_buffers/axi_interconnect_buffers/mi_register_slice_bank/gen_reg_slot[9].register_slice_inst/aw_pipe/storage_data1_56
------------------------------------------------- ---------------------------
Total 6.182ns (0.340ns logic, 5.842ns route)
(5.5% logic, 94.5% route)
--------------------------------------------------------------------------------
Slack (setup path): -0.004ns (requirement - (data path - clock path skew + uncertainty))
Source: microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Byte_Doublet_Handle_gti_I/MEM_DataBus_Write_Data_25 (FF)
Destination: warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/PktTemplate1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_init.ram/NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram (RAM)
Requirement: 6.250ns
Data Path Delay: 6.127ns (Levels of Logic = 0)
Clock Path Skew: -0.069ns (1.454 - 1.523)
Source Clock: axi_bram_ctrl_0_BRAM_PORTA_0_BRAM_Clk rising at 0.000ns
Destination Clock: axi_bram_ctrl_0_BRAM_PORTA_0_BRAM_Clk rising at 6.250ns
Clock Uncertainty: 0.058ns
Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.092ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Byte_Doublet_Handle_gti_I/MEM_DataBus_Write_Data_25 to warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/PktTemplate1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_init.ram/NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
---------------------------------------------------- -------------------
SLICE_X114Y174.DQ Tcko 0.322 axi_interconnect_periph_160_M_wdata<102>
microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Byte_Doublet_Handle_gti_I/MEM_DataBus_Write_Data_25
RAMB36_X3Y16.DIBDI6 net (fanout=242) 5.554 axi_interconnect_periph_160_M_wdata<102>
RAMB36_X3Y16.CLKBWRCLKL Trdck_DIB 0.251 warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/PktTemplate1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_init.ram/NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram
warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/PktTemplate1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_init.ram/NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram
---------------------------------------------------- ---------------------------
Total 6.127ns (0.573ns logic, 5.554ns route)
(9.4% logic, 90.6% route)Offline
The only suspicious thing I did is I added quite a lot (~130) new register readings from memory (inside Memory-based Registers).
This is very likely to be the cause of the timing failure. Every readable register adds a port to the read mux in the core's bus interface. 130 is a lot - can you reduce the number of registers? If you're using registers to read many values from the core, a better architecture could be using a single "Shared Memory" block. Your logic can write values to the RAM, then software can access those values by reading offsets into the RAM. This architecture only adds one port to the read mux (the RAM's data_out port), so is more likely to meet timing.
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