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For our demand, we need a board based on FPGA which can provide at least 4 Radio Boards. Besides, we want to utilize the clock synthetizer on this board.
My senario is to use a clock buffer "ICS8442"(IDT.corp) which uses an crystal oscillator as input (we will use an TCXO) and provide a wide rang output with 2.7ps' RMS jitter and 18ps' cycle-to-cycle jitter(both are typical). And besides, since ICS8442 can just provide two differential clock output we also need another clock buffer to spread up to more clock outputs to support more Radio Boards.
I just want to know is there any possible problems in our senario?
Thanks,
Sam Liu
Last edited by samliu (2008-Oct-20 04:38:46)
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Are you thinking of using the WARP radio board driven by a different clock source (not the WARP clock board)? The radio reference clock fed to the WARP FPGA board is 20MHz. The transceiver (MAX2829) uses its own PLL to generate the RF carrier anywhere in 2400-2500MHz and 4900-5875MHz. These are the only frequency ranges supported by the transceiver.
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You are right. We are just thinking of using our own clock board and also we will not use the WARP FPGA board. We need our own FPGA board which can provide sampling clock to Radio Board. And our system will just contain a FPGA board and some Radio Boards.
I find that we can solder a TCXO on the Radio Board for MAX2829 and just need a sampling clock which we will sythesize it by ICS8442. We just hope this scenario will be fine.
Thanks,
Sam Liu
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As long as the sampling clock is in the range 1-65MHz (requirement of the AD9248-65), it should work.
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