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In your ofdm_txrx_mimo.mdl, the antennae are modeled as top-level Xilinx Gateway In ports, with no reference to FPGA pin designation. How do interface to the receiver in hardware from the Simulink block? Do you define the pins after converting the Simulink block to VHDL, or is there a way to inform Matlab of the pin designations that I am not seeing?
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The port connections among different peripheral cores are none of Simulink's concern. You will find the port connections for the ofdm core, as well as every other peripheral, in the system.mhs file of the reference design's XPS project. Specifically, the input ports of the ofdm core are routed to the output ports of the radio bridges through the AGC core. Radio bridge ports in turn are mapped to the actual FPGA pins through the system.ucf assignments.
Last edited by Amir (2008-Dec-03 20:10:38)
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