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Hello RICE,
We would like to implement a spectrum sensing simulink model and then integrate it with the OFDMreference design 11. To do this we would have to get the IQ samples as input to my SpectrumSensing model. Can you give me some reference codes which is already using the IQ samples from the radio board and we could use these IQ samples as a starting point to our SpectrumSensing model.
Do you have any comments/feedback on this integration of spectrumSensing model to OFDMreference design 11.
-Ragha
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The I/Q values are available at outputs from the radio_bridge pcores. The AGC and PHY cores (ofdm_agc_mimo and ofdm_txrx_mimo) both connect to these ports. You can add a third pcore that uses the same signals. The WARPLab Sysgen core would be another good example.
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Hello Murpho,
Thank you very much for the info. It was very helpful.
B.Wishes
Ragha
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Hello Murpho,
We tried to run the warplab_mimo_2x2.mdl file from the warpLab tutorial that was available in the warpRepository (and also which is available here The WARPLab Sysgen core), and we got the following errors. Please suggest methods to correct this.
###############################################
An internal error occurred in the Xilinx Blockset Library.
Please report this error to Xilinx (http://support.xilinx.com), in as much detail as possible. You may also find immediate help in the Answers Database and other online resources at http://support.xilinx.com.
Error occurred during "Block Configuration".
This block is currently unlinked in the Simulink model. System Generator does not guarantee that unlinked blocks will work properly. Relinking the block in the model may correct this error.
Reported by:
'warplab_mimo_2x2/Mem_Control/AddSub1'
#####################################################
regards,
Ragha
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Hello Rice,
In continuation with the query when i run the ofdm_txrx_mimo.mdl from the reference design OFDM_ReferenceDesign_v11 i get the following errors
###################
Error reported by S-function 'sdspsigattrib' in 'dummyIQ/OFDM Rx MIMO/Equalizer & Packetizer/Phase Adjust/Post-PhaseAdj/Is Discrete/Check Signal Attributes':
Continuous sample times not allowed.
###################
Please suggest a solution.
thanks
-Ragha
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What version of MATLAB are you using? And do you have the latest Sysgen release installed ('xlversion' in MATLAB should return 10.1.3.1386), and the latest version of ISE (10.1, IP Update 3 and Service Pack 3)?
For the second error, see this previous post.
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Hi Murpho,
Apparently we have the xlversion 10.1.3.1386 and the 10.1, IP Update 3 and Service Pack 3. Off late i had linked matlab 2008 version to XPS but recently i have linked matlab 2007a to XPS could this cause any problem (logically it should not, but just thinking of reasons to explain the anomaly).
-Ragha
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Hi Murpho,
It was my bad i had loaded the warplab_mimo_2x2.mdl file from wrong location i.e instead of
C:\WARP_Repository\ResearchApps\PHY\WARPLAB\WARPLab_MIMO2x2_MIMO4x4_R04\Sysgen_MIMO_2x2
i loaded it from
C:\WARP_Repository\ResearchApps\PHY\WARPLAB\WARPLab_MIMO2x2_MIMO4x4\Sysgen_MIMO_2x2
Now it is resolved!
thanks,
Ragha
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Interesting. Both are valid Sysgen models, though version v04 is newer (and saved using Systen 10.1.03, I believe). Anyway, glad it's working.
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Hello RICE,
In continuation of our effort to
1) Make a Simulink model using "radio2_adc_i" and "radio2_adc_q" as input and a "64 bit value stored in a register/shared memory" as output
2) Add the Simulink model as a pcore.
3) Making the operation of this Simulink Model as Interrupt based and enabling/disabling the interrupt using a C-program Initializing code.
4) Use the Output of the Simulink model in a C-Program.
So far we have done the first 2 steps
Can you please suggest us how we can go about the 3rd and the 4th step ?
thanks,
Ragha
PS: we are trying out the "Xilinx : Creating and Adding Custom peripheral option"
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Have you worked through the tutorials- especially "Designing Custom Peripherals" and "Using a Custom Peripheral in XPS"? These will walk you through the entire flow of designing a peripheral and configurating it via a C program. You can complete the design even if you don't have a kit with an analog board (you just won't be able to try it in hardware).
Lab 3 from our latest workshop is also a good example of designing a pcore in Sysgen.
As for step (3), I suggest learning to use interrupts independent of a custom pcore. Xilinx provides an app note (xapp778) with some examples. The section describing the opb_intc is the most useful. If you're using XPS 10.1, this core was replaced by the xps_intc, but it uses the same hardware/software conventions. Our OFDM reference design uses this core extensively, handling interrupts from both Xilinx and custom (Sysgen-designed) pcores. All of the interrupt setup/handling code is part of WARPMAC.
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Hello Murpho,
Thank you very much for the detailed information and sorry for the late response. We went through the tutorials and the workshops and modeled our SpectruSense module based on those guide lines.
We were stuck up in reading the (8 bit / 16 bit / 32 bit of the "From-register/ shared memory) memories after writing into them.
Problem 1:
a) For a single variable i.e lets say unsigned 16 bit number
We were writing value "N" in the memory but when we read the value was "0" always
b) For an array of any size more than one i.e lets say unsigned 16 bit number
when We write value "N" in the memories array[0],array[1].....etc and read the value, we usually get the correct results i.e "N".
but, later found out that in case a: the value "N" was actually written into the memory but we could not read it for some reason.
@RICE :- Is it some kind of known error! even otherwise any suggestions would be great.
Problem 2:
a) We are directly using the outputs of Radio 2 ADC I and Radio 2 ADC Q to get the IQ samples are we doing this right (given that our aim is to get the IQ samples and process them).
regards,
Ragha
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1) If you're using the latest version of Sysgen (10.1.03.1386, as reported by xlversion in MATLAB), From registers aren't software readable by default. You have to enable this in the EDK Processor block, in the Implementation tab; check the box 'Enable Register Readback'. You will need to re-export the pcore and re-build the XPS project.
2) Capturing the raw I/Q samples is fine. It is possible to grab the raw signals coming from the radio. But we definitely recommend using the user_ADC* ports on the radio bridge pcore. This allows the radio bridge to instantiate registers that get packed into the IOBs, which help with timing during PAR. Other than delaying the samples 1 cycle (in the IOB registers), the radio bridge doesn't alter them in any way. This is exactly how WARPLab works.
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Hello RICE,
We enabled the "Register Readback" and now we are able to read the value, thanks for the suggestion.
As per your recommendation we used the user_ADC* ports and we seem to be getting the IQ values properly but we will confirm the results later.
Problem:
1) We have problem in using the fprintf(); function (also fopen(); fwrite(); and others)
-are there any alternatives like xil_printf(); (for printf();) function to be able to perform the above operation.
thanks,
Ragha
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xil_printf() is the only replacement I know of. And it's basically printf() without support for floating point values (saving a lot of code space).
We haven't used fprintf/fopen/fwrite/etc. In the context of the standalone OS, where there's no file system, what would these functions do?
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Dear all, Could any tell me how to pull out the data from user_ADC* ports as mentioned in post #13. I saw this port in VHDL in the pcore but have no idea how to print out the data in C++.
Thanks,
Chen-Wei
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The user_ADC ports represent hardware connections in the FPGA fabric. They are accessed by other cores in the FPGA. The WARPLab Sysgen core and OFDM PHY design are two examples; both connect to the user_ADC and user_DAC ports on the radio bridges. If you want to access raw I/Q samples from C code, I would suggest starting with the WARPLab Reference Design.
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