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How can I connect some of the signals of my model to the general purpose pins of the FPGA for debugging purposes? I don't see any unconnected ports in the external ports section of the ports specification.
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The debug I/O on the FPGA board isn't included in the XBD, because the port directions & widths aren't known ahead of time. You can create your own top-level port in XPS ('Add External Port' button in the Ports view).
You will have to add pin location constraints for any ports you create. You can find the proper pin locations using the FPGA board pinout spreadsheet from the repository. Look on the second worksheet ('Other Pins') for the Digital I/O signals.
On the FPGA board, the pins are routed to the 20-pin 100-mil connector in the upper-right corner. On this connector, the four corner pins are ground. The middle 16 pins are numbered [0-15], the same as the entries in the spreadsheet.
For an example of how to use this header, take a look at the XPS project for the OFDM reference design. We use top-level debug ports for idle/running signals in the receiver and transmitter, packet detection & good/bad packet interrupt, etc.
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I tried to setup some debug pins, but am not able to figure out where to assign pin locations. I looked up the OFDM model, but don't see any pin location specifications for some of the debug pins. Should the pin locations be set in System Generator or in XPS? If it is XPS how do you set pin location constraints. When I add external pin, there is no place to set the constraint.
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It's a multi-step process to bring a signal out to one of the debug pins. For an example, look at the OFDM Reference Design project.
The OFDM core in this design has a handful of 1-bit outputs used for debug. Each of these is a gateway out in the Sysgen design, which map to top-level ports in the resulting pcore. Open system.mhs and look for the OFDM core port 'rx_debug_payload' on line 533. This port is tied internally to signal 'debug_rx_payload'. This signal is routed to a top level port named 'debug' (line 155), which is a vector output composed of many 1-bit debug signals. This port will become a top-level port (i.e. pins) in system.vhd, the auto-generated top-level HDL file integrating the full XPS hardware project.
To use the FPGA board's debug pins, you have to constrain the location of this top-level output. Look at data/system.ucf from the reference design. The debug bus is constrained on lines 45-53, mapping its 9 bits to the first 9 pins on the debug header.
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Thanks. My question was specifically, where do you constrain the pin locations?
murphpo wrote:
To use the FPGA board's debug pins, you have to constrain the location of this top-level output. Look at
data/system.ucf from the reference design. The debug bus is constrained on lines 45-53, mapping its 9 bits to the first 9 pins on the debug header.
Do I really need to edit the ucf file or is there a way in XPS to specify this info. I know there is a way in System Generator to do this. You can click on the gateways and specify IOB locations. However, I seem to be getting some weird errors when I do this. I was wondering what you guys did. I suppose you edited the .ucf file.
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Ok. I see your point now. There is no automatic way of transferring/consolidating constraints from SysGen to XPS. The data/system.ucf is the consolidated constraints file generated by XPS and the only way to update such pin loc constraints is to edit this file.
Thanks.
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