You are not logged in.
Hey,
How to get the FPGA data into the computer for debug purpose. It is better to avoid power PC and ethernet protocol in this case for simplicity. If possible, could you post the necessary setup (including tools and cables) and procdures for FPGA debug and data retrieval?
Have you guys tried SysGen hardware-software co-simulation with WARP?
Thanks.
Last edited by zrcao (2007-Apr-14 15:34:55)
Offline
Your best bet for in-FPGA debug is Xilinx's ChipScope. We use this extensively to debug our OFDM receiver cores.
We haven't used hardware co-simulation with the current generation of hardware. However, Sysgen's JTAG co-simulation flow should be straightforward to use on the WARP FPGA board. This flow is described in the System Generator User's Guide (pg. 199). You'll need to know some of the pin assignments on the board; refer to the FPGA board's pinout spreadsheet for this info.
Offline
Is it possible for you to give a little more detailed setup description for using ChipScope. For example, should we use USB and JTAG at the same time? USB for download the bitstream and JTAG for chipscope? Also, in building the SysGen model, we should including the chipscope block. Is there any parameter settings we should pay attention to?
We haven't use chipscope before, since we had a platform with good memory saving support to record all the run time data for post processing.
Thanks.
Last edited by zrcao (2007-Apr-15 16:40:58)
Offline
For learning how to use ChipScope, I'd suggest Xilinx's ChipScope documentation. The Sysgen user's guide also describes how to use ChipScope in Sysgen designs (pg. 350).
The USB configuration port on the FPGA board is a JTAG connection. You can't use both the USB port and 14-pin Parallel-IV connector at the same time. ChipScope Analyzer (just like iMPACT) will recognize the USB connection as a standard JTAG connection to the FPGA.
Offline
We are testing chipscope right now. A question pops up:
Do we have to use SysGen2OPB to generate the pcore and build the bit file in EDK, even for a simple model without any data/control exchange with PPC via the OPB bus?
Offline
In fact, there are two more general questions
1. Do we have to use EDK if we only use the FPGA part of the WARP Virtex II pro? Can't we build the bitstream in SysGen token and download into the WARP using another way?
2. For a pcore without OPB connection, such as the radio bridge, what is the procedure to include it into EDK project? If we do not include a from/to reg in the model, sysgen2opb refuses to convert. One the other hand, there is no reason to call sysgen2opb in this case if there is not OPB connection.
Last edited by zrcao (2007-Apr-16 20:08:34)
Offline
ChipScope can be used in any FPGA design, with any FPGA board that has a JTAG connection. It does not require the EDK or Sysgen. However both the EDK and Sysgen support using ChipScope to debug designs.
The only automatic way to create a pcore from a Sysgen design is with sysgen2opb. It should be possible to create a pcore manually from a Sysgen netlist using the EDK's Create/Import Peripheral Wizard, though I've never tried this.
Remember also that the PowerPC and EDK are required to use the radio controller core, which itself is required to use the WARP radio board. The radio board has a bunch of control signals and initialization requirements that are handled by calls to the radio controller's software driver.
Offline
So how did you generate the pcore "radio_bridge"? It is not an OPB peripheral. I guess you wrote HDL code and translate it into pcore, right?
Offline
Right- we wrote the Verilog source by hand, then created the MPD and PAO files using the Create/Import Peripheral Wizard. We only used the wizard for the first version. The syntax of both files is easy enough that we updated them manually when we changed the underlying Verilog.
Offline
Thanks.
Offline