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Hi
Is there any way to synchronize two warp nodes on clock using the reference design code or do we need to do it explicitly using some synchronization mechanisms.
Thanks
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There are two ways:
-You can use the FPGA board's digital I/O to share a trigger signal between nodes. This is great for "faking" a wireless synchronization scheme, for prototyping slotted/scheduled medium access for example. Each pin on the header can be defined as a top-level port, connected to whatever FPGA core you want. See the OFDM reference design hardware project for an example. Here, we use 10 outputs for monitoring various events (good/bad packet completions, timer expiration). There's also 1 input used as a debug trigger.
-You can share the system clocks between nodes using coax cables between clock boards. The clock board drives both the radio reference clock (20MHz) and sampling clock (40MHz) for the node. You can select whether it derives each clock from its on board oscillators or from another clock board via its off-board connection. You'll need an MMCX-MMCX cable to use the inter-clock-board connections. Refer to the clock board users guide for details and connector mappings.
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