You are not logged in.
Hi there, I am an enthusiastic newbie to WARP boards and after reading some old forum posts I'm still not sure what is the right answer to my question:
what is the available sampling rate on the radio board (rev 1.4) (in Rx mode)? Is it fixed at 40msps by the off-board 40MHz signal coming from the clock board (rev 1.1) ?
My understanding is that, as of rev 1.4, it is NOT possible to change the sampling rate (I wanted to lower it) with the clock sources available from the standard kit, correct?
I got confused because I read the following on reply #2 of on http://warp.rice.edu/forums/viewtopic.php?id=18
___________
"With the current version of the hardware, the FPGA board has a single 100 MHz oscillator feeding a global clock pin on the FPGA. The FPGA uses a DCM to derive the clock signals used elsewhere in the system. This includes the 50 MHz ADC/DAC clock for the radio board, the 200 MHz PowerPC clock, 100 MHz PLB clock and 50 MHz OPB clock. You can customize the frequencies of all of these clocks by modifying the configuration of the dcm_module in your XPS design. "
___________
What is this "50 MHz ADC/DAC clock for the radio board" ? Isn't it 40Mhz?
Thanks a lot!
Greeting from RWTH-Aachen in Germany.
Last edited by osunax (2009-Sep-03 10:10:41)
Offline
That forum post refers to a previous generation of hardware before the clock board, when we used FPGA-generated clocks for sampling and oscillators mounted on the radio board for the carrier reference. All modern kits (including the ones at RWTH-Aachen) use a fixed 40MHz sampling clock driven by the clock board's 40MHz TCXO. You can adjust the effective sampling rate digitally (using rate-change filters in the FPGA, to adapt a digital waveform of smaller bandwidth to a 40MHz sampling rate). You can also drive an external clock signal into the clock board (using connector J3; see the users guide for details). In this setup, you need to honor the min/max sampling rate of the radio board's ADC (1MHz min, 65MHz max; see the AD9248 datasheet for details) and the FPGA logic in your design.
Offline
Thanks for the prompt reply and clarification. Ok, I'll look into the rate-change filters in the FPGA... does this mean that the signal is actually still sampled at 40Msps but it is then adjusted to a different rate in the FPGA before further processing? ...how do I tweak these rate-change filters? with SysGen?
My initial goal is to do a non-real time design flow (i.e. using WARPLab to process the samples I get from the radio board). Does it then make sense to look into lowering the sampling rate with this rate-change-filters option? I mean, can I limit the real-time design to just adjusting the sampling rate and then pass the "adjusted" samples onto WARPLAB for further processing?
Offline
osunax wrote:
Thanks for the prompt reply and clarification. Ok, I'll look into the rate-change filters in the FPGA... does this mean that the signal is actually still sampled at 40Msps but it is then adjusted to a different rate in the FPGA before further processing?
Yes, exactly. The DAC/ADC are always clocked at 40MHz, and any interpolation/decimation is handled in the FPGA. You can see examples of this in our OFDM PHY, where we use 4x interpolation at the Tx output (to achieve 10MHz over-the-air bandwidth when sampled at 40MHz). In our Simple Streaming reference design, we have both 8x interpolation and decimation filters. All these filters are implemented in System Generator and could be added to the WARPLab core for your application.
Offline