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If I'm right the bandwidth of the Reference design is 10MHz. We want to increase the bandwidth to 20MHz (similar to WLAN).
Which actions have to be taken to do so. I can imagine this is not that easy, but can you give an indication where the bottlenecks are. We currently use Reference design v12.1 in SISO and 2x2 multiplexing mode.
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You are correct, the output bandwidth is 10MHz. Currently the design is built as follows: The OFDM core is clocked at 40MHz and the output samples are at 10MHz. This ratio is fixed in the sysgen design. To increase your bandwidth to 20MHz you will need to either clock the OFDM core at 80MHz or change the sysgen pipeline to output samples at twice the rate.
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Also, the radio boards are clocked at 40MHz. So if you do change the rate at which the OFDM core clock to 80MHz you will need to modify the output interpolation filter to rate 2 instead of rate 4.
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Have you ever tried this?
Bringing the OFDM core to 80MHz, does that mean increasing the plb_32b_40MHz plb-bus to 80MHz. Then also the other peripherals on that bus (like AGC and radio controller) will run at that speed. Do these blocks then also require some modifications?
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Yes the plb_32b_40MHz must move to 80MHz correct. The radio controller generates an internal clock that is used for SPI access. This clock cannot be faster than 40MHz In order for the radio controller to work at 80MHz use the clkRatio of 2 (API) when calling the reset function. The AGC should also work at 80MHz.
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