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According to posts (1) and (2), I tried again to show RSSI data on RS232. I am able to reuse the old version of radio controller and radio bridge. Unfortunately, I still couldn't get a reasonable RSSI output.
The project I built only include opb_uartlite for RS232, radio_controller_0 v1.07a and radio_bridge_2 with v1.07a. Also, I set to use Serial input to control the Rx gain. The SMA connect is left open or terminated. I also use function WarpRadio_RxLNAGainControl to switch the LNA from high gain to middle gain to low gain. Besides, I tried in software to turn on/off Rx or turn on/off Tx.
However, for both boards we have and in any setting I tried, the RSSI reading is always 896 or 968. The value changes after I re-program the FPGA, but does not change during runtime even I use WarpRadio_RxLNAGainControl to modify the LNA settings. Interestingly, if I program the FPGA right after power on the WARP board, the RSSI reading is always 0. I have to re-program the system in order to see a value around 900.
Does above description ring a bell? I am still scrutinizing my codes and settings. But if needed, I will post my code and .mhs files.
Thank you very much.
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Are you driving a clock to the RSSI ADC converter (via the user_RSSI_ADC_clk input port on the radio bridge)? A user core must supply this clock signal. The packet detector core does this in our OFDM designs (described here)
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Oo....ops! I forgot this. Will try soon.
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