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Hello.
I note that the Processor clock frequency is set to 240Mhz
and Bus clock frequency is set to 80Mhz in the "WARPLab_ReferenceDesign_2x2_v05_02_FPGAv2".
However, these settings are different with those in "http://warp.rice.edu/trac/wiki/peripheral_test/sw_setup" .
The question are as follows:
If we use v2 kit, just setting them to 240M and 80M?
If we use v1 kit, just setting them to 100M and 50M?
Thanks.
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A few things:
-There's no difference in clocking requirements between v1 and v2 kits.
-All of the clocks in a project are derived from a single oscillator. This can either be the 100MHz oscillator on the FPGA board or the 40MHz oscillator on the clock board.
-If you're using the Radio Boards, you must use the 40MHz oscillator as the primary clock source (so that the FPGA logic will be synchronous with the ADC/DAC sampling clocks, which are derived from the same 40MHz oscillator).
-The 'peripheral_test' tutorial you mentioned uses the FPGA board's 100MHz oscillator (it doesn't use the Clock Board or Radio Boards), hence the internal FPGA clocks that are fractions/multiples of 100MHz.
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Thanks for your response: )
I still have a question about the lab: "WARPLab_2x2_v05_02_FPGAv2"
The follow is the comment in the mhs file:
# Created by Base System Builder Wizard for Xilinx EDK 10.1.03 Build EDK_K_SP3.6
# Sat Oct 10 15:03:40 2009
# Target Board: Rice University - WARP Project WARP Kits (FPGA/Clock/Radio Boards) Rev FPGA 2.2 / Radio 1.4 / Clock 1.1
# Family: virtex4
# Device: XC4VFX100
# Package: FF1517
# Speed Grade: -11
# Processor: ppc405_0
# Processor clock frequency: 240.00 MHz
# Bus clock frequency: 80.00 MHz
# On Chip Memory : 96 KB
I got a question about the clock frequency setting: We can see that the Processor clock frequency isn't set to 100Mhz, and Bus clock frequency isn't set to 50Mhz.
To verify the clock, I take a experiment by setting Processor Clock freq=240Mhz, Bus clock freq=80Mhz, and set the UART_DB9 baudrate as 57600. This experiment works fine because I observed that the baud rate is actually about 58000 bps by oscilloscope.
For another question, if I set the Processor clock frequency as 100 MHz and Bus clock frequency as 80 MHz,
It said that Memory cannot be selected for current frequency so I couldn't choose the SDRAM peripheral in BSB.
Thanks very much . Squall
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The SDRAM controller uses the MPMC core, which has very particular clocking requirements. You'll need to read the MPMC datasheet (click the Datasheet button next to the core in Base System Builder) to understand what combinations of clocks are valid. WARPLab and the OFDM Reference Design don't use the MPMC; both designs require only on-chip memory.
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Thanks for your response : ) It works fine .
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