WARP Project Forums - Wireless Open-Access Research Platform

The platform itself doesn't even require MATLAB. The only tool which is always required is Xilinx ISE; this is the only way to target the platform's FPGA. If you're interested in low-level, stright HDL FPGA design, this is all you'll need.

Our PHY designs are built in MATLAB/Simulink using Xilinx System Generator. Sysgen doesn't require any extra toolboxes or blocksets. Having the communications blockset is helpful, though, in simulating and debugging PHY designs.

Our wireless reference designs make extensive use of the Xilinx Embedded Devleopment Kit. This is the tool used to integrate custom logic designs with the embedded PowerPC cores in the FPGA. The EDK includes a bunch of Xilinx IP cores, some of which we use in the reference designs (UART, general-purpose I/O, interrupt controller, memory controllers, etc.).

The only IP core we use which is not included in the EDK is the PLB Ethernet MAC. The EDK includes an evaluation copy which works normally in hardware for something like 7 hours before disabling itself. Re-downloading a bitstream to the FGPA restarts this timer, so even this isn't much of a restriction for prototyping and experimentation work. Like the other Xilinx cores, universities can generally request a donation of the unlocked PLB EMAC.

All of the IP cores used in the OFDM PHY are included with ISE and are wrapped as Sysgen blocks for use in Simulink. Most of the PHY, including the comm stuff like modulation & filtering, is built using low-level blocks (mostly arithmetic, logical & memory blocks).

The PHY is currently uncoded. Xilinx's FEC cores are not included with the tools, though universities can generally request a donation of the cores from Xilinx.