WARP Project Forums - Wireless Open-Access Research Platform

The best place to start with this customization is to directly modify the w3_warplab_buffers.mdl core. The source model is in the repository: /ResearchApps/PHY/WARPLAB/WARPLab7/Sysgen_Reference/w3/warplab_buffers.

The w3_warplab_buffers.mdl core implements the interface between the ADCs and sample buffers, and between the sample buffers and DACs. In the reference design the core does not implement any signal processing in either direction. If your application requires taking an FFT of all received samples, you can modify the w3_warplab_buffers pipeline to be ADC->FFT->sample buffers. Then when your m code retrieves samples via the usual WARPLab commands, it will receive the output of your pipeline (i.e. the FFT of the ADC samples), instead of the raw samples stored in the ref design.

If you are not familiar with the System Generator / XPS design flow, please start with our tutorials. These exercises introduce the same tools used by the WARPLab and 802.11 Reference Designs, using a much simpler design. Once you're comfortable with exporting a Sysgen core to XPS and re-building the XPS project, you can use this flow to iterate on a custom WARPLab design.

Correct, you should not need to change the C code.  If you update the buffers core, then all of the processing will occur on the sample stream and should be completed before the information is placed in memory to be read out via Read IQ.

Your steps are basically correct.  A couple of notes:

  1) Your updated warplab buffers pcore should have the same ports as the previous pcore (for WARP v3, we use the AXI bus standard vs the PLB bus standard).  So when you replace the warplab buffers pcore in the pcores folder of the EDK project, you should only need to update the revision number in the MHS file (I would make sure that you use a different revision number when updating the pcore so you are sure you are getting the correct one).  Basically, changing the revision number should be all the "hook up" you need to do.

  2) You need to be careful that you don't alter the timing of control signals.  Please study how the warplab buffers core works in terms of addressing / IQ data storage.  If you delay the sample data in the pipeline due to additional processing, just understand that there will be some padding samples at the front of the buffer depending on the processing delay. 

  3) Understand the debug capabilities of the warplab buffers pcore.  There are two main debug features in the core:  a) RX data generator; b) TX to RX data loopback.  You can see how to enable them in the wl_baseband.h header file.  Also, there is a "simulation" mode in the pcore (see w3_warplab_buffers_init.m) that allows you to easily configure register values to perform a simulation (just remember to make sure that simulation is set to 0 when generating your pcore).  These features are extremely useful for getting your pcore working.  The RX data generator uses a counter to generate fake RX data and the TX to RX data loopback allows you to have a "perfect" reception of the Tx waveform you set with Write IQ (i.e. since the data never goes through the RF ports, there is not modification of the data from Tx to Rx).

1)  The buffers core starts when it receives a pulse on "trigger_in".  This comes from the trigger manager and occurs after the TX/RX trigger is received.  The trigger input starts both the transmit and receive state machines. 

2)  For WARP v3, the data is stored in a tiered way (this is how we are able to increase the buffer sizes in WARPLab 7.5.x for WARP v3).  First, as you can see in the FPGA architecture, the warplab buffers core has direct access to BRAM blocks that it uses to temporarily read / store samples.  The TX / RX state machines generate CPU interrupts when the buffers reach a given threshold.  This causes the CPU to transfer the contents of the BRAM to the DDR where the actual buffer lives.

3)  I'm not quite sure I understand the issue.  The buffer that you create in Matlab that is pushed to the node via Write IQ has a 1-to-1 correspondence with the contents of the buffer on the node.  Regardless of the processing that you perform on the TX or RX stream of samples, the buffer that you pushed to the node to transmit will be the buffer processed by the core.  Now, depending on the amount of processing, there will be some number of samples at the beginning of the RX waveform that need to be ignored.  However, this is already the case in the current version of WARPLab given the delays in the RF frontend and the fact that most of the examples start the TX and RX state machines at the same time.  You will just need to ignore more samples in the beginning of the RX waveform.  Now, if your TX and RX buffers are the same size, you run into a situation where the tail end of the TX waveform is not caputred.  If this is the case, then you shouldn't put important data at the very end of the TX waveform.  However, one of the nice things you can do with WARPLab 7.5 is make your RX buffer much longer than your TX buffer so that you always capture the entire TX waveform.

I am using ISE design suite 14.4.
In system generator, the parameters I choose is as follows:
Compilation: Export as a pcore to EDK
Part: Virtex6 xc6vlx240t-2ff1156
Sythesis tool: XST
Hardware description language: VHDL
Target directory: ./w3_warplab_buffers
Others: default

I've added IFFT and FFT in the transmitting and receving side respectively and produced new system.bit file in the directory of "\implementation". What's the next step? (1) or (2)?
(1) copy system.bit file to "\SDK_Workspace\w3_WARPLab_EDK_4RF_v7.5.1_hw_platform", start SDK to generate a new linker script and download the design to the board.
(2) click "Export & Launch SDK." in XPS, and copy software from directories needed.

Thanks a lot.

1. lack of some files in "*_bsp_0/microblaze_0/libsrc"
    When I tried to generate new BSP in SDK, I found that I miss some directories in directory "*_bsp_0/microblaze_0/libsrc" compared with reference design WARPv3_lab7.5.1

 1. w3_warplab_agc_axiw_v_3_b
          2. w3_warplab_buffers_axiw_v3_01_c
          3. w3_warplab_trigger_proc_axiw_v1_04_b
          4. WARP_FPGA_BOARD_LIB_v2_20_a
          5. WARP_HW_VER_v3_10_a
          6. WARPxilnet_v3_04_a

2. An extra  file in "*_bsp_0/microblaze_0/libsrc"

 1. generic_v1_00_a

3. The number of head file in "*_bsp_0/microblaze_0/include"
        There are only 70 items instead of 85 items.

[img]D:\xzha\EDK_problem.png[/img]

When I create Xilinx BSP, the setting is like :

        --------------------+------------+--------------------------------------
        Name                |Version     |                    Description
        --------------------+------------+--------------------------------------
 |X|    WARP_FPGA_BOARD_LIB |1.20.a      |WARP FPGA Board v1.2 Software Library
        --------------------+------------+--------------------------------------
 |X|    WARP_HW_VER         |1.20.a      |WARP Hardware Version Library - WARP v1.2
        --------------------+------------+--------------------------------------
 |X|    WARPxilnet          |2.00.a      |WARP/Xilinx Networking TCP/IP stack library
        --------------------+------------+--------------------------------------
        lwip140             |1.03.a      |  ....
        --------------------+------------+--------------------------------------
        xilfatfs            |1.00.a      |  ....
        --------------------+------------+--------------------------------------
        xilflash            |3.03.a      |  ....
        --------------------+------------+--------------------------------------
        xilisf              |3.00.a      |  ....
        --------------------+------------+--------------------------------------
        xilmfs              |1.00.a      |  ....
        --------------------+------------+--------------------------------------

obviously, I need to check the first three libraries, however, the version is not the latest. How could I fix it?

I have changed the module "w3_warplab_buffers" to implement interpolation and decimation.  Unfortunately, it seemed that the desired logic did not function properly after I download the "bin" file into the SD card.  My design is based on WARPLab7.5.1.
What I've done involves:
1. changed the design using Xilinx System Generator
2. FIR5.0 Xilinx Blockset is used for interpolation and decimation filter. ( The phase delay is 39 clocks, thus the whole system produces 78-clock delay than the reference design)
3. RTL simulation is done using Questasim and the outcome is correct.
4. XPS and EDK flow are correct because of past successful experience.

Matlab script to be run : "wl_example_siso_ofdm_txrx.m".
I am unable to get correct constellation even if INTERP_RATE is set to 2.

Therefore, I want to do gate-level simulation to find out what happened after Place and Route. Could you please tell me how to get the gate-level netlist and sdf file after XPS flow?