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#1 2016-Apr-27 05:50:40

Registered: 2013-Dec-31
Posts: 12

warp v3 board

hello All

I am new to this warp v3 board,everything what i studied is pretty well written and understood by me,but one this is confusing me i:e

'' The RF interface clocking design is centered on two AD9512 2-to-5 clock buffers.''

but as i see on the board there is only one AD9512 clock buffer,So why they are showing it as two in diagram shown under topic clocking in warp website.

please help me out.



#2 2016-Apr-27 09:05:25

From: Mango Communications
Registered: 2006-Jul-03
Posts: 5159

Re: warp v3 board

There are two AD9512 buffers, one on top (U20) that distributes the RF reference clocks and one on bottom (U46) that distributes the sampling clocks. Both circuits are implemented on page 15 of the WARP v3 schematics.



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