WARP Project Forums - Wireless Open-Access Research Platform

You are not logged in.

#1 2016-Mar-30 18:35:04

Warp_User_New
Member
Registered: 2016-Mar-30
Posts: 5

FPGA Design Flow

Hi,

I have designed a system using Verilog in ISE which contains both Verilog files of my own and ip cores generated by Core Generator of ISE (Mainly Block Rams). I want to test my system on WARP boards. Is there anyway to run my design in a WARP based system? If yes, where to start? Are there any tutorials for this case?

The most important point is how I should modify my design to cope with available WARP projects.

In addition, I need to read data through Ethernet port from a host in my design. How is that possible in WARP setting?


Thank you,

Offline

 

#2 2016-Mar-31 09:12:33

welsh
Administrator
From: Mango Communications
Registered: 2013-May-15
Posts: 612

Re: FPGA Design Flow

I would suggest that you start with the Getting Started Guide.  This has an Introduction to Xilinx Tools that should be helpful.  For each of the reference designs, we release both the MHS and UCF files which can be modified to integrate your additions.

Ethernet communication depends on the reference design you are planning to use.  From the node side, we have built the WARP IP/UDP Library to provide low-level Ethernet packet processing.  You can see an example of how we interact with the library in wlan_exp_transport.c.  For the host side, in the 802.11 Reference design, we have built a Python transport to communicate with the node.  In the WARPLab reference design, we have built a Matlab transport that can use MEX to communicate with the node.

Offline

 

#3 2016-Mar-31 14:51:25

Warp_User_New
Member
Registered: 2016-Mar-30
Posts: 5

Re: FPGA Design Flow

Is it possible for me to read the data directly from Ethernet to my core? It seems communication with Ethernet is through MicroBlaze. If this is true, Should I read the data sent from host into MicroBlaze and then send it to my core using software instructions in MicroBlaze?

Offline

 

#4 2016-Apr-01 04:12:53

murphpo
Administrator
From: Mango Communications
Registered: 2006-Jul-03
Posts: 5159

Re: FPGA Design Flow

You can design custom logic that interfaces directly to the four AXI Stream interfaces of the axi_etherent core (AXI_STR_RXD, AXI_STR_RXS, AXI_STR_TXD and AXI_STR_TXC). The axi_ethernet datasheet describes these interfaces in detail. You will still need a MicroBlaze to configure the axi_ethernet core via its memory-mapped (S_AXI) interface.

Building the custom hardware design described above is certainly possible, but it is a big project. You might have more luck integrating your custom logic with the WARPLab Reference Design and re-using WARPLab's existing infrastructure for moving data between the WARP node and host PC. This is definitely a good approach if your custom logic generates streams of "samples" (whether actual I/Q samples or values that can be treated as samples). We need to know more about your design and requirements to provide any more specific suggestions.

Offline

 

#5 2016-Apr-01 16:55:20

Warp_User_New
Member
Registered: 2016-Mar-30
Posts: 5

Re: FPGA Design Flow

Thanks,

My design is not a communication project. From time to time, I require my modules to receive some data from host and send some data back after some computations. Should I handle the handshaking signaling in my module? I don't get how "WARPLab's existing infrastructure for moving data between the WARP node and host PC" should be made use of?

Assume a simple modules that every 20ms reads two 16bit numbers and sends their sum after 10ms back to host. I have a ISE project that does this. How to add this to existing to WARPLab Reference Design? I mean what else should I implement in my module to be able to be added to your reference design (To be able to communicate with host through Ethernet)?

Any help would be appreciated!

Last edited by Warp_User_New (2016-Apr-03 11:15:27)

Offline

 

#6 2016-Apr-04 05:05:07

murphpo
Administrator
From: Mango Communications
Registered: 2006-Jul-03
Posts: 5159

Re: FPGA Design Flow

If you only require communicating one 32-bit value every 20 msec, I would suggest using the UART. The UART is slow but easy to use.

If your design has a MicroBlaze subsystem you can use the axi_uartlite core; this is how we implement the UART interface in our 802.11 and WARPLab Reference Designs.

If you do not have a CPU in your system you would need to implement a simple UART interface in your HDL. There are many example UART implementations out there (i.e. osdvu, Simple UART, etc.). On WARP v3 the FPGA-UART interface is 2 pins (Tx and Rx). The USB-UART controller on the board handles everything else internally.

Offline

 

#7 2016-Apr-04 09:06:03

welsh
Administrator
From: Mango Communications
Registered: 2013-May-15
Posts: 612

Re: FPGA Design Flow

Given the data rate, I would suggest Patrick's approach using the UART.  However, if you must use Ethernet, then you should look at how to extend WARPLab or how to extend wlan_exp for the 802.11 Reference design.  This will allow the Microblaze to get the values from the Ethernet packet; communicate those values to your peripheral; retrieve a result; and finally send the result back to the host.

Offline

 

#8 2016-May-02 16:24:30

Warp_User_New
Member
Registered: 2016-Mar-30
Posts: 5

Re: FPGA Design Flow

Thanks for your information.

I still can't get if I can design my system in verilog and implement it as a core in WARPLab framework. Is it possible?

Also, can MicroBlaze soft-cores of two WARP boards talk to each other using the IP/MAC address of each other? Is there any available code in C for Microblaze cores to do such a data transfer?

I want to use the WARP boards for the following purpose. There are a number of WARP boards that are connected to each other using Ethernet. First a PC host programs them by loading bitstream into FPGAs. Then inside each FPGA, user-defined core starts processing data stored in DDR3 RAM and from time to time Microblaze inside the FPGA, sends the data stored in the DDR3 RAM to other FPGAs directly (not through the host PC). 

Are the currently available reference designs suitable for the above system? Specifically, I want to send data stored in DDR3 RAMs of a FPGA by using available functions (Are the functions in wl_transport.h suitable for this purpose?) to other FPGAs and they will receive these and store them in their own DDR3 RAM (Are the functions in wl_common.h (CDMA transfer) suitable for this purpose?) by using available functions.

If this data transmission is not possible in my desired manner between 2 WARP boards, Is it possible between a WARP board and the host PC?

Thank you for your comprehensive reply in advance.

Last edited by Warp_User_New (2016-May-02 22:24:49)

Offline

 

#9 2016-May-03 10:40:47

murphpo
Administrator
From: Mango Communications
Registered: 2006-Jul-03
Posts: 5159

Re: FPGA Design Flow

I still can't get if I can design my system in verilog and implement it as a core in WARPLab framework. Is it possible?

Yes. Custom HDL can be wrapped in a pcore and integrated in the WARPLab Reference Design XPS project. The Xilinx ISE tools provide the 'Create/Import Peripheral Wizard' to assist with creating pcore templates and wrapping custom HDL as pcores.

Also, can MicroBlaze soft-cores of two WARP boards talk to each other using the IP/MAC address of each other? Is there any available code in C for Microblaze cores to do such a data transfer?

We have not implemented this behavior, but it's certainly possible.

The WARPLab Reference Design uses our WARP_ip_udp library to implement its ARP/IP/UDP stack. This library only implements UDP server behaviors- it listens for UDP-encapsulated commands from MATLAB (WARPLab ref design) or Python (wlan_exp in 802.11 ref design) and sends UDP-encapsulated responses from the node. In this context the MATLAB/Python code acts as the UDP client. If you want two nodes to communicate directly via IP/UDP you would need to modify the C code of the library and application to implement UDP client behaviors.

I want to use the WARP boards for the following purpose. There are a number of WARP boards that are connected to each other using Ethernet. First a PC host programs them by loading bitstream into FPGAs. Then inside each FPGA, user-defined core starts processing data stored in DDR3 RAM and from time to time Microblaze inside the FPGA, sends the data stored in the DDR3 RAM to other FPGAs directly (not through the host PC). 

Are the currently available reference designs suitable for the above system? Specifically, I want to send data stored in DDR3 RAMs of a FPGA by using available functions (Are the functions in wl_transport.h suitable for this purpose?) to other FPGAs and they will receive these and store them in their own DDR3 RAM (Are the functions in wl_common.h (CDMA transfer) suitable for this purpose?) by using available functions.

Again, this behavior is possible but is not implemented in the reference code. You will not find functions in wl_transport.h for this. In order to build this behavior you will need to study the existing code and modify it to implement your new functionality.

If this data transmission is not possible in my desired manner between 2 WARP boards, Is it possible between a WARP board and the host PC?

I would definitely suggest starting with this simpler approach. The WARPLab 'read_iq' command implements a fast 'get data from DRAM' process. The 'write_iq' command implements a fast 'write data to DRAM' process.

Offline

 

#10 2016-May-03 11:02:49

Warp_User_New
Member
Registered: 2016-Mar-30
Posts: 5

Re: FPGA Design Flow

Thanks.

what are the purposes of functions such as transport_send or transport_poll in wl_transport?

Using write_iq/read_iq I will be able to write/read data to DDR RAMs, So I would not even require the microblaze to handle the data movement between nodes and host. Is this right?

One other question, mostly related to hardware, Do you think if I use HLS to design my core inside the fpga, I will be able to integrate it with your reference design?

Last edited by Warp_User_New (2016-May-03 11:56:28)

Offline

 

#11 2016-May-04 09:54:02

murphpo
Administrator
From: Mango Communications
Registered: 2006-Jul-03
Posts: 5159

Re: FPGA Design Flow

Using write_iq/read_iq I will be able to write/read data to DDR RAMs, So I would not even require the microblaze to handle the data movement between nodes and host. Is this right?

No. In the WARPLab Reference Design the MicroBlaze CPU coordinates all DMA data transfers to/from DRAM, processes all received Ethernet packets, creates all outgoing Ethernet packets, etc. All of this is implemented in the reference C code which runs in the MicroBlaze core.

One other question, mostly related to hardware, Do you think if I use HLS to design my core inside the fpga, I will be able to integrate it with your reference design?

It is possible to use older versions of HLS (<2016.1) to build cores for Virtex-6 devices (ref). We have no experience with this design flow. The Xilinx HLS/ISE documentation is your best resource for exploring this option.

Offline

 

Board footer