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I tried to get started with the FMC-BB-4DA by adding the fmc_bb_4da_bridge_0 core to the WARPLab 7.1.0 design. Therefore, I added the configuration from http://warp.rice.edu/trac/wiki/cores/fmc_bb_4da_bridge to the system.mhs and the system.ucf file. To be able to have a clock and a 90 degree shifted clock I attached the 40 MHz clock CLKOUT2 to sys_samp_clk and CLKOUT3 to sys_samp_clk_90. The user_DAC_A...D inputs are now connected to warplab_buffers::rfa_dac_i, rfa_dac_q, rfb_dac_i, rfb_dac_q.
The intension is to observe the transmitted baseband signals using an oscilloscope. Unfortunately, it does not work. When I measure the output signals on the FMC_BB_4DA board, they all stay at constant random values.
Can someone please advice me how to get started with the FMC-BB-4DA. For the development I use the Xilinx tools in version 14.4
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It sounds like you hooked everything up right. Can you double check vs. the code snippets below? These are from a known-working project using the FMC-BB-4DA (the full XPS project is available here, part of the Rice ELEC 433 course materials).
Top-level ports in system.mhs:
#FMC-BB-4DA pins PORT DAC_AB_DB = DAC_AB_DB, DIR = O, VEC = [0:13] PORT DAC_CD_DB = DAC_CD_DB, DIR = O, VEC = [0:13] # DAC_AB clock/control PORT DAC_AB_CLK = DAC_AB_CLK, DIR = O PORT DAC_AB_RESET = net_vcc, DIR = O PORT DAC_AB_CSN = net_gnd, DIR = O PORT DAC_AB_SCLK = net_gnd, DIR = O PORT DAC_AB_SDIO = net_vcc, DIR = O # DAC_CD clock/control PORT DAC_CD_CLK = DAC_CD_CLK, DIR = O PORT DAC_CD_RESET = net_vcc, DIR = O PORT DAC_CD_CSN = net_gnd, DIR = O PORT DAC_CD_SCLK = net_gnd, DIR = O PORT DAC_CD_SDIO = net_vcc, DIR = O
fmc_bb_4da_bridge instance in system.mhs:
BEGIN fmc_bb_4da_bridge PARAMETER INSTANCE = fmc_bb_4da_bridge_0 PARAMETER HW_VER = 1.00.a PARAMETER INCLUDE_IDELAYCTRL = 0 PARAMETER DAC_AB_CLK_ODELAY_TAPS = 31 PARAMETER DAC_CD_CLK_ODELAY_TAPS = 31 PORT sys_samp_clk = clk_40MHz PORT sys_samp_clk_90 = clk_40MHz_90degphase PORT user_DAC_A = net_gnd PORT user_DAC_B = net_gnd PORT user_DAC_C = net_gnd PORT user_DAC_D = net_gnd PORT DAC_AB_DB = DAC_AB_DB PORT DAC_CD_DB = DAC_CD_DB PORT DAC_AB_CLK = DAC_AB_CLK PORT DAC_CD_CLK = DAC_CD_CLK END
LOC constraints in system.ucf:
#FMC-BB-4DA NET "DAC_AB_CLK" LOC = H20 | IOSTANDARD = LVCMOS25; #FMC_LA09_N NET "DAC_AB_RESET" LOC = F21 | IOSTANDARD = LVCMOS25; #FMC_LA00_CC_P NET "DAC_AB_CSN" LOC = B20 | IOSTANDARD = LVCMOS25; #FMC_LA01_CC_P NET "DAC_AB_SCLK" LOC = G20 | IOSTANDARD = LVCMOS25; #FMC_LA00_CC_N NET "DAC_AB_SDIO" LOC = E22 | IOSTANDARD = LVCMOS25; #FMC_LA02_P NET "DAC_AB_DB<13>" LOC = F20 | IOSTANDARD = LVCMOS25; #FMC_LA07_N NET "DAC_AB_DB<12>" LOC = A24 | IOSTANDARD = LVCMOS25; #FMC_LA08_N NET "DAC_AB_DB<11>" LOC = F19 | IOSTANDARD = LVCMOS25; #FMC_LA07_P NET "DAC_AB_DB<10>" LOC = E21 | IOSTANDARD = LVCMOS25; #FMC_LA05_N NET "DAC_AB_DB<9>" LOC = A23 | IOSTANDARD = LVCMOS25; #FMC_LA08_P NET "DAC_AB_DB<8>" LOC = G22 | IOSTANDARD = LVCMOS25; #FMC_LA06_N NET "DAC_AB_DB<7>" LOC = D21 | IOSTANDARD = LVCMOS25; #FMC_LA05_P NET "DAC_AB_DB<6>" LOC = D19 | IOSTANDARD = LVCMOS25; #FMC_LA04_N NET "DAC_AB_DB<5>" LOC = G21 | IOSTANDARD = LVCMOS25; #FMC_LA06_P NET "DAC_AB_DB<4>" LOC = E19 | IOSTANDARD = LVCMOS25; #FMC_LA04_P NET "DAC_AB_DB<3>" LOC = C23 | IOSTANDARD = LVCMOS25; #FMC_LA03_N NET "DAC_AB_DB<2>" LOC = B23 | IOSTANDARD = LVCMOS25; #FMC_LA03_P NET "DAC_AB_DB<1>" LOC = C19 | IOSTANDARD = LVCMOS25; #FMC_LA01_CC_N NET "DAC_AB_DB<0>" LOC = E23 | IOSTANDARD = LVCMOS25; #FMC_LA02_N NET "DAC_CD_CLK" LOC = F13 | IOSTANDARD = LVCMOS25; #FMC_LA28_N NET "DAC_CD_RESET" LOC = D20 | IOSTANDARD = LVCMOS25; #FMC_LA11_N NET "DAC_CD_CSN" LOC = H13 | IOSTANDARD = LVCMOS25; #FMC_LA16_N NET "DAC_CD_SCLK" LOC = G12 | IOSTANDARD = LVCMOS25; #FMC_LA16_P NET "DAC_CD_SDIO" LOC = G13 | IOSTANDARD = LVCMOS25; #FMC_LA15_P NET "DAC_CD_DB<13>" LOC = E13 | IOSTANDARD = LVCMOS25; #FMC_LA28_P NET "DAC_CD_DB<12>" LOC = J10 | IOSTANDARD = LVCMOS25; #FMC_LA29_N NET "DAC_CD_DB<11>" LOC = J11 | IOSTANDARD = LVCMOS25; #FMC_LA29_P NET "DAC_CD_DB<10>" LOC = D11 | IOSTANDARD = LVCMOS25; #FMC_LA24_P NET "DAC_CD_DB<9>" LOC = D12 | IOSTANDARD = LVCMOS25; #FMC_LA25_P NET "DAC_CD_DB<8>" LOC = B13 | IOSTANDARD = LVCMOS25; #FMC_LA21_N NET "DAC_CD_DB<7>" LOC = A11 | IOSTANDARD = LVCMOS25; #FMC_LA26_P NET "DAC_CD_DB<6>" LOC = B12 | IOSTANDARD = LVCMOS25; #FMC_LA21_P NET "DAC_CD_DB<5>" LOC = A14 | IOSTANDARD = LVCMOS25; #FMC_LA22_N NET "DAC_CD_DB<4>" LOC = E14 | IOSTANDARD = LVCMOS25; #FMC_LA19_N NET "DAC_CD_DB<3>" LOC = J12 | IOSTANDARD = LVCMOS25; #FMC_LA20_N NET "DAC_CD_DB<2>" LOC = F14 | IOSTANDARD = LVCMOS25; #FMC_LA19_P NET "DAC_CD_DB<1>" LOC = H12 | IOSTANDARD = LVCMOS25; #FMC_LA20_P NET "DAC_CD_DB<0>" LOC = H14 | IOSTANDARD = LVCMOS25; #FMC_LA15_N
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I just noticed this example uses the older fmc_bb_4da_bridge (1.00.a), which doesn't manage the DAC control signals. It might still be worth a try. I've tested the fmc_bb_4da_bridge 1.00.b successfully, but don't have access to that project at the moment (I'm away from the office this week).
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Hello murphpo,
thank you very much for your quick answer. I managed to get the core running by connecting the DAC inputs to some registered that are writable by the processor. So far version 1.00.a works, now I am generating the design for 1.00.b and then I will find the problem, why the output of the warplab_buffers didn't work.
Matthias
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Hi murphpo,
What's the standard of interfaces of DAC outputs? It looks unlike the SMA standard, sort of smaller...?
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The FMC-BB-4DA module has 1 MCX jacks per analog output (this is documented in the user guide).
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