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#1 2017-Jan-05 22:10:39

Rather
Member
Registered: 2016-Oct-25
Posts: 28

Pseudo Random Sequence

Hello everyone,

I do have a basic confusion about Core implementation on Warp V3.


I want to create a Simple multiplier core in Simulink  and then display the result on the HEX DISP. The input to multiplier i want to be in variable state.

I just need to know do this design also require to have a microblaze processor from xilinx?

The Pseudo-random example i have successfully implemented this way and generated .bit file and got the result. Does pseudo-random example uses that Microblaze core for its implementation?

if yes,then cannot we implement a simple multiplier or a pseudo-random generator directly on a blank FPGA.


Please help with this one?

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#2 2017-Jan-06 09:56:47

murphpo
Administrator
From: Mango Communications
Registered: 2006-Jul-03
Posts: 5159

Re: Pseudo Random Sequence

I want to create a Simple multiplier core in Simulink  and then display the result on the HEX DISP. The input to multiplier i want to be in variable state.

You can use the System Generator Bitstream export flow for this design. In this flow System Generator creates the full FPGA design, synthesizes and implements the design, then writes a bitstream that can be programmed to the board. This flow does not create any MicroBlaze processors and does not use the XPS or SDK tools. To use this flow you must specify the FPGA pins of each Gateway In/Out in the design. Refer to the WARP v3 pinout constrains for pin assignments. You must also specify the master clock input. I would recommend the 200MHz LVDS oscillator input (called 'OSC_SYSCLK1_P/OSC_SYSCLK1_N' in the constraints).

We do not have a tutorial for this, as there are many Sysgen tutorials online and in the Xilinx documentation.

Keep in mind this design flow will not use the peripherals on the WARP v3 board (RF interfaces, memory, Ethernet). All of these peripherals require interface cores of their own. The interface cores we use (radio_controller, w3_ad_controller, w3_clock_controller, axi_ddrx, axi_ethernet) require a design with a MicroBlaze CPU and use of each core's C drivers.

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