WARP Project Forums - Wireless Open-Access Research Platform

In that case, what will be the maximum distance between two boards (i.e. the maximum length of the coaxial cable)?

The max length depends on many parameters (quality of the coax cable & connectors, interference sources along the cable, etc). The clock inputs on the AD9512 buffers (the clock distribution IC on the WARP v3 board) are fairly sensitive, requiring only 150mVp-p to operate at spec. We have seen cables >10m work fine, but can't guarantee this for all cables.

For the output of CM-MMCX, what is the difference between "RF ref" and "Samp ref"? I try to use both as the external reference signal for a CM-PLL module, it seems both output can drive the CM-PLL (successfully boot up to display the ID on 7-segment displays). If I want to use a CM-MMCX as master clock to drive a CM-PLL module, which output I should use?

The RF Ref input drives the MAX2829 reference clock inputs. The Samp ref input drives the ADC/DAC clock reference and the FPGA. The CM-MMCX supports different inputs/outputs for these clocks. However in most applications the RF and sampling reference clocks should be synchronous (often driven by the same clock). The CM-PLL drives both clocks from a single oscillator whose frequency is controlled by a single reference clock (typically driven by an off-board reference source).

Either CM-MMCX output is electrically/mechanically compatible with the CM-PLL reference input. However you must adjust the frequency of either the CM-MMCX output or the CM-PLL configuration accordingly. Our reference designs configure the PLL on the CM-PLL module for a 10MHz reference input. Refer to the user guide for more details.

Actually, I am a little bit confused about the difference between "RF ref" and "Samp ref".

This is explained in the WARP v3 user guide clocking section. The WARP v3 PCB has separate clock distribution circuits for the radio reference and sampling reference clocks. By default both distribution circuits are driven by the same 80MHz TCXO.

Can I use both output from a CM-MMCX to synchronize two other boards equipped with CM-PLL modules?

Yes, but this configuration cannot be achieved using just the switches on the clock modules - you will need to modify the design source code.

I would encourage you to start by reviewing the available docs:
-CM-MMCX user guide
-CM-PLL user guide
-WARP v3 clocking
-w3_clock_config core

Then draw a diagram of what connections you plan to make between modules and what clock frequency each connection will use. From there you can modify the source code to achieve the selections of inputs, outputs and frequencies you need.

One approach would be to configure both CM-MMCX outputs as 10MHz driving the MMCX inputs on two CM-PLL modules. To achieve 10MHz outputs from the CM-MMCX you must change the C code to enable the outputs and set the dividers:

// Configure clock module header outputs as 10MHz (80MHz / 8)
clk_config_dividers(CLK_BASEADDR, 8, CLK_SAMP_OUTSEL_CLKMODHDR | CLK_RFREF_OUTSEL_CLKMODHDR);

// Enable Sampling and RF Ref clock outputs to clock module header
clk_config_outputs(CLK_BASEADDR, CLK_OUTPUT_ON, (CLK_SAMP_OUTSEL_CLKMODHDR | CLK_RFREF_OUTSEL_CLKMODHDR));

If you're using WARPLab the clock configuration code is in node_clk_initialize() in wl_node.c.